Patents by Inventor Benjamin P. Smith

Benjamin P. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240137130
    Abstract: An optical receiver includes an error generator, a multipath interference estimator, and a combiner. The error generator is configured to receive an input comprising a received optical signal, to estimate a modulation level of samples of the received optical signal, and to generate an error signal based on the estimated modulation level of the samples, the error signal representing a difference between an actual level of the received optical signal and the estimated modulation level. The multipath interference estimator is configured to generate estimates of multipath interference (MPI) associated with the samples of the received optical signal based on the error signal. The combiner is configured to generate an MPI-mitigated signal based on a combination of the samples and the estimates of MPI.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 25, 2024
    Inventors: Benjamin P. SMITH, Jamal RIANI, Sudeep BHOJA, Arash FARHOODFAR, Vipul BHATT
  • Patent number: 11916574
    Abstract: A receiver includes an error correction module. A syndrome value, calculated based on received signals, may be used to enable the error correction module. The error correction module includes an error generator, a Nyquist error estimator, and a decoder. The decoder uses error estimation generated by the Nyquist error estimator to correct the decoded data. There are other embodiments as well.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: February 27, 2024
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Benjamin P. Smith, Jamal Riani
  • Publication number: 20230421180
    Abstract: A communication device includes a convolutional interleaver and an encoder. The convolutional interleaver is configured to receive blocks of data defining symbol blocks that are encoded using a block code to correct an error in a block of data and to interleave the symbol blocks into a stream of interleaved symbol blocks. The encoder is configured to encode a set of symbol blocks among the interleaved symbol blocks with an error-correcting code to correct single bit errors in the set of symbol blocks. The error-correcting code is configured to generate an error-correcting block and to add the error-correcting block to the set of interleaved symbol blocks.
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Inventors: Benjamin P. SMITH, Volodymyr Shvydun, Jamal Riani, Ilya Lyubomirsky
  • Patent number: 11855702
    Abstract: A circuit and method for mitigating multi-path interference in direct detection optical systems is provided. Samples of an optical signal having a pulse amplitude modulated (PAM) E-field are processed by generating a PAM level for each sample. For each sample, the sample is subtracted from the respective PAM level to generate a corresponding error sample. The error samples are lowpass filtered to produce estimates of multi-path interference (MPI). For each sample, one of the estimates of MPI is combined with the sample to produce an interference-mitigated sample.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: December 26, 2023
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Benjamin P. Smith, Jamal Riani, Sudeep Bhoja, Arash Farhoodfar, Vipul Bhatt
  • Patent number: 11764811
    Abstract: A communication device includes interleaver circuitry that receives, from a host device, a first encoded data stream comprised of a plurality of symbols encoded with a first type of error correction code and interleaves the plurality of symbols of the first encoded data stream into symbol sections each including a predetermined number of symbols encoded with the first type of error correction code. Encoder circuitry encodes the first encoded data stream in accordance with a second type of error correction code different from the first type of error correction code by generating, for each of the symbol sections, an error code block corresponding to the symbols in the symbol section and outputs a second encoded data stream including the first encoded data stream and the error code block.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: September 19, 2023
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Benjamin P. Smith, Volodymyr Shvydun, Jamal Riani, Ilya Lyubomirsky
  • Patent number: 11575396
    Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 7, 2023
    Assignee: MARVELL ASIA PTE LTD.
    Inventors: Jamal Riani, Farshid Rafiee Rad, Benjamin P. Smith, Yu Liao, Sudeep Bhoja
  • Patent number: 11575391
    Abstract: The present invention is directed to communication systems and methods. According to a specific embodiment, FEC data streams from multiple FEC data lanes are received. First stage interleaving and inner encoding are performed on the FEC data streams to generate inner encoded data streams. A second stage interleaving process is performed to interleave the inner encoded data streams. There are other embodiments as well.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: February 7, 2023
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Benjamin P. Smith, Ilya Lyubomirsky
  • Publication number: 20220376712
    Abstract: The present invention is directed to communication systems and methods. In a specific embodiment, the present invention provides a receiver that includes an error correction module. A syndrome value, calculated based on received signals, may be used to enable the error correction module. The error correction module includes an error generator, a Nyquist error estimator, and a decoder. The decoder uses error estimation generated by the Nyquist error estimator to correct the decoded data. There are other embodiments as well.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 24, 2022
    Inventors: Benjamin P. SMITH, Jamal RIANI
  • Publication number: 20220302928
    Abstract: The present invention is directed to communication systems and methods. According to a specific embodiment, FEC data streams from multiple FEC data lanes are received. First stage interleaving and inner encoding are performed on the FEC data streams to generate inner encoded data streams. A second stage interleaving process is performed to interleave the inner encoded data streams. There are other embodiments as well.
    Type: Application
    Filed: March 18, 2021
    Publication date: September 22, 2022
    Inventors: Benjamin P. SMITH, Ilya LYUBOMIRSKY
  • Publication number: 20220302930
    Abstract: A communication device includes interleaver circuitry that receives, from a host device, a first encoded data stream comprised of a plurality of symbols encoded with a first type of error correction code and interleaves the plurality of symbols of the first encoded data stream into symbol sections each including a predetermined number of symbols encoded with the first type of error correction code. Encoder circuitry encodes the first encoded data stream in accordance with a second type of error correction code different from the first type of error correction code by generating, for each of the symbol sections, an error code block corresponding to the symbols in the symbol section and outputs a second encoded data stream including the first encoded data stream and the error code block.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Benjamin P. SMITH, Volodymyr SHVYDUN, Jamal RIANI, Ilya LYUBOMIRSKY
  • Patent number: 11405134
    Abstract: An optical module processes first FEC (Forward Error Correction) encoded data produced by a first FEC encoder. The optical module has a second FEC encoder for further coding a subset of the first FEC encoded data to produce second FEC encoded data. The optical module also has an optical modulator for modulating, based on a combination of the second FEC encoded data and a remaining portion of the first FEC encoded data that is not further coded, an optical signal for transmission over an optical channel. The second FEC encoder is an encoder for an FEC code that has a bit-level trellis representation with a number of states in any section of the bit-level trellis representation being less than or equal to 64 states. In this manner, the second FEC encoder has relatively low complexity (e.g. relatively low transistor count) that can reduce power consumption for the optical module.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 2, 2022
    Assignee: MARVELL ASIA PTE LTD.
    Inventors: Benjamin P. Smith, Arash Farhoodfar
  • Patent number: 11368170
    Abstract: The present invention is directed to communication systems and methods. In a specific embodiment, the present invention provides a receiver that includes an error correction module. A syndrome value, calculated based on received signals, may be used to enable the error correction module. The error correction module includes an error generator, a Nyquist error estimator, and a decoder. The decoder uses error estimation generated by the Nyquist error estimator to correct the decoded data. There are other embodiments as well.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: June 21, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Benjamin P. Smith, Jamal Riani
  • Publication number: 20220173814
    Abstract: A circuit and method for mitigating multi-path interference in direct detection optical systems is provided. Samples of an optical signal having a pulse amplitude modulated (PAM) E-field are processed by generating a PAM level for each sample. For each sample, the sample is subtracted from the respective PAM level to generate a corresponding error sample. The error samples are lowpass filtered to produce estimates of multi-path interference (MPI). For each sample, one of the estimates of MPI is combined with the sample to produce an interference-mitigated sample.
    Type: Application
    Filed: February 17, 2022
    Publication date: June 2, 2022
    Inventors: Benjamin P. SMITH, Jamal Riani, Sudeep Bhoja, Arash Farhoodfar, Vipul Bhatt
  • Patent number: 11258518
    Abstract: A circuit and method for mitigating multi-path interference in direct detection optical systems is provided. Samples of an optical signal having a pulse amplitude modulated (PAM) E-field are processed by generating a PAM level for each sample. For each sample, the sample is subtracted from the respective PAM level to generate a corresponding error sample. The error samples are lowpass filtered to produce estimates of multi-path interference (MPI). For each sample, one of the estimates of MPI is combined with the sample to produce an interference-mitigated sample.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: February 22, 2022
    Assignee: MARVELL ASIA PTE LTD.
    Inventors: Benjamin P. Smith, Jamal Riani, Sudeep Bhoja, Arash Farhoodfar, Vipul Bhatt
  • Patent number: 11245493
    Abstract: The present invention relates to data communication systems and methods thereof. More specifically, embodiments of the present invention provide a data transmission method. Data are encoded with staircase encoder, and staircase coded blocks are first interleaved then combined into outer code frames. Code frames additionally include sync words and padding bits. A second interleaving is applied to the bits of the code frames, and Hamming encoding is performed on the output of the second interleaver. Hamming codewords are Gray-mapped to dual-polarized quadrature-amplitude-modulation (DP-QAM) symbols, and a third interleaving of the symbols from a set of successive Hamming codewords is performed. Pilot symbols are inserted periodically into the stream of DP-QAM symbols. There are other embodiments as well.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: February 8, 2022
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Benjamin P. Smith, Jamal Riani, Arash Farhoodfar, Sudeep Bhoja
  • Patent number: 11239991
    Abstract: The present invention is directed to circuits and communication. More specifically, a specific embodiment of the present invention provides a timing recovery device with two stages. The first stage generates a clock signal to sample the received waveform, and the second stage provides timing-jitter mitigation. The second stage includes a jitter mitigation circuit with coefficients a function of the instantaneous jitter estimate, in addition to a jitter estimation tracking loop consisting of an error generator, a timing error detector and a loop filter to compensate for timing jitter associated with the clock signal. There are other embodiments as well.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: February 1, 2022
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Benjamin P. Smith, Jamal Riani
  • Publication number: 20210336761
    Abstract: The present invention is directed to circuits and communication. More specifically, a specific embodiment of the present invention provides a timing recovery device with two stages. The first stage generates a clock signal to sample the received waveform, and the second stage provides timing-jitter mitigation. The second stage includes a jitter mitigation circuit with coefficients a function of the instantaneous jitter estimate, in addition to a jitter estimation tracking loop consisting of an error generator, a timing error detector and a loop filter to compensate for timing jitter associated with the clock signal. There are other embodiments as well.
    Type: Application
    Filed: April 28, 2020
    Publication date: October 28, 2021
    Inventors: Benjamin P. SMITH, Jamal RIANI
  • Publication number: 20210306009
    Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Inventors: Jamal RIANI, Farshid RAD, Benjamin P. SMITH, Yu LIAO, Sudeep BHOJA
  • Patent number: 11038538
    Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: June 15, 2021
    Assignee: INPHI CORPORATION
    Inventors: Jamal Riani, Farshid Rafiee Rad, Benjamin P. Smith, Yu Liao, Sudeep Bhoja
  • Publication number: 20210111833
    Abstract: An optical module processes first FEC (Forward Error Correction) encoded data produced by a first FEC encoder. The optical module has a second FEC encoder for further coding a subset of the first FEC encoded data to produce second FEC encoded data. The optical module also has an optical modulator for modulating, based on a combination of the second FEC encoded data and a remaining portion of the first FEC encoded data that is not further coded, an optical signal for transmission over an optical channel. The second FEC encoder is an encoder for an FEC code that has a bit-level trellis representation with a number of states in any section of the bit-level trellis representation being less than or equal to 64 states. In this manner, the second FEC encoder has relatively low complexity (e.g. relatively low transistor count) that can reduce power consumption for the optical module.
    Type: Application
    Filed: December 18, 2020
    Publication date: April 15, 2021
    Inventors: Benjamin P. SMITH, Arash FARHOODFAR