Patents by Inventor Benjamin T. Voegeli
Benjamin T. Voegeli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8946013Abstract: A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.Type: GrantFiled: February 2, 2012Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Natalie B. Feilchenfeld, Jeffrey P. Gambino, Xuefeng Liu, Benjamin T. Voegeli, Steven H. Voldman, Michael J. Zierak
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Patent number: 8686478Abstract: Methods of electrically programming a diffusion resistor by using trapped charge in a trapped charge region adjacent to the resistor to vary the resistance of the resistor, and the resistor, are disclosed. In one embodiment, a method includes forming a diffusion resistor in a substrate; forming a trapped charge region adjacent to the diffusion resistor; and adjusting a resistance of the diffusion resistor by controlling the trapped charge in the trapped charge region.Type: GrantFiled: November 14, 2011Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Benjamin T. Voegeli, Kimball M. Watson
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Patent number: 8525293Abstract: High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.Type: GrantFiled: May 15, 2012Date of Patent: September 3, 2013Assignee: International Business Machines CorporationInventors: Natalie B. Feilchenfeld, Bradley A. Orner, Benjamin T. Voegeli
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Patent number: 8493250Abstract: A successive approximation analog-to-digital converter (ADC) includes an adjustable voltage source that applies an adjustable voltage to an input of a comparator of the ADC to cancel an offset of the ADC. The ADC also includes a control that suspends adjustments of the adjustable voltage when the adjustable voltage converges on the offset. The adjustable voltage source is a digital-to-analog converter.Type: GrantFiled: September 7, 2011Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Anthony R. Bonaccio, Frank R. Keyser, III, Benjamin T. Voegeli
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Publication number: 20130057417Abstract: A successive approximation analog-to-digital converter (ADC) includes an adjustable voltage source that applies an adjustable voltage to an input of a comparator of the ADC to cancel an offset of the ADC. The ADC also includes a control that suspends adjustments of the adjustable voltage when the adjustable voltage converges on the offset. The adjustable voltage source is a digital-to-analog converter.Type: ApplicationFiled: September 7, 2011Publication date: March 7, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony R. BONACCIO, Frank R. KEYSER, III, Benjamin T. VOEGELI
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Publication number: 20120319233Abstract: High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.Type: ApplicationFiled: May 15, 2012Publication date: December 20, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Natalie B. Feilchenfeld, Bradley A. Orner, Benjamin T. Voegeli
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Patent number: 8302037Abstract: A differential system producing differential signals with offset cancellation utilizing a double differential input pair system is disclosed. It uses two parallel differential transistor pairs which are intentionally skewed. Nominally, the differential pairs are skewed in opposite direction from each, but with equal magnitude, so that the combination of the two differential pairs is nominally balanced. The current through each differential pair is then increased or decreased until any offset is sufficiently cancelled, using a selection means for providing an equi-potential value to first and second differential inputs in a calibration mode of the system and a comparison means for comparing first and second differential outputs in a calibration mode to determine the offset of the system.Type: GrantFiled: June 30, 2009Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Igor Arsovski, Anthony R Bonaccio, Hayden (Clay) Cranford, Jr., Joseph A Iadanza, Pradeep Thiagarajan, Sebastian T Ventrone, Benjamin T Voegeli
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Patent number: 8236662Abstract: High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.Type: GrantFiled: November 18, 2010Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Natalie B. Feilchenfeld, Bradley A. Orner, Benjamin T. Voegeli
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Publication number: 20120126319Abstract: A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.Type: ApplicationFiled: February 2, 2012Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Natalie B. Feilchenfeld, Jeffrey P. Gambino, Xuefeng Liu, Benjamin T. Voegeli, Steven H. Voldman, Michael J. Zierak
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Publication number: 20120058611Abstract: Methods of electrically programming a diffusion resistor by using trapped charge in a trapped charge region adjacent to the resistor to vary the resistance of the resistor, and the resistor, are disclosed. In one embodiment, a method includes forming a diffusion resistor in a substrate; forming a trapped charge region adjacent to the diffusion resistor; and adjusting a resistance of the diffusion resistor by controlling the trapped charge in the trapped charge region.Type: ApplicationFiled: November 14, 2011Publication date: March 8, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benjamin T. Voegeli, Kimball M. Watson
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Patent number: 8125019Abstract: An electrically programmable resistor is presented. In one embodiment, a resistor includes a doped body within a substrate; a trapped charge region adjacent to the resistor, the resistance of the resistor controlled by an amount of trapped charge in the trapped charge region.Type: GrantFiled: October 18, 2006Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Benjamin T. Voegeli, Kimball M. Watson
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Patent number: 8114750Abstract: A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.Type: GrantFiled: April 17, 2008Date of Patent: February 14, 2012Assignee: International Business Machines CorporationInventors: Natalie B. Feilchenfeld, Jeffrey P. Gambino, Xuefeng Liu, Benjamin T. Voegeli, Steven H. Voldman, Michael J. Zierak
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Patent number: 7972919Abstract: The present invention relates to a device structure located in a semiconductor substrate and containing high performance vertical NPN and PNP transistors. Specifically, the vertical PNP transistor has an emitter region, and the vertical NPN transistor has an intrinsic base region. The emitter region of the vertical PNP transistor and the intrinsic base region of the vertical NPN transistor are located in a single silicon germanium-containing layer, and they both contain single crystal silicon germanium. The present invention also relates to a method for fabricating such a device structure based on collateral modification of conventional fabrication processes for CMOS and bipolar devices, with few or no additional processing steps.Type: GrantFiled: July 18, 2005Date of Patent: July 5, 2011Assignee: International Business Machines CorporationInventors: Peter B. Gray, Benjamin T. Voegeli
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Patent number: 7956412Abstract: A dielectric material layer is formed on a bottom surface and sidewalls of a trench in a semiconductor substrate. The silicon oxide layer forms a drift region dielectric on which a field plate is formed. Shallow trench isolation may be formed prior to formation of the drift region dielectric, or may be formed utilizing the same processing steps as the formation of the drift region dielectric. A gate dielectric layer is formed on exposed semiconductor surfaces and a gate conductor layer is formed on the gate dielectric layer and the drift region dielectric. The field plate may be electrically tied to the gate electrode, may be an independent electrode having an external bias, or may be a floating electrode. The field plate biases the drift region to enhance performance and extend allowable operating voltage of a lateral diffusion field effect transistor during operation.Type: GrantFiled: December 4, 2007Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Natalie B. Feilchenfeld, Jeffrey P. Gambino, Louis D. Lanzerotti, Benjamin T. Voegeli, Steven H. Voldman, Michael J. Zierak
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Publication number: 20110062548Abstract: High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.Type: ApplicationFiled: November 18, 2010Publication date: March 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Natalie B. Feilchenfeld, Bradley A. Orner, Benjamin T. Voegeli
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Patent number: 7892910Abstract: High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.Type: GrantFiled: February 28, 2007Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Natalie B. Feilchenfeld, Bradley A. Orner, Benjamin T. Voegeli
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Patent number: 7886240Abstract: Modifying a layout of an integrated circuit (IC) based on a function of an interconnect therein and a related circuit and design structure are disclosed. In one embodiment, a method includes identifying a function of an interconnect in the layout from data of the layout embodied in a computer readable medium; and modifying the layout to form another layout that accommodates the function of the interconnect. A design structure embodied in a machine readable medium used in a design process, according to one embodiment, may include a circuit including a high voltage interconnect positioned in a dielectric layer, the high voltage interconnect positioned such that no fill is above or below the high voltage interconnect.Type: GrantFiled: January 29, 2008Date of Patent: February 8, 2011Assignee: International Business Machines CorporationInventors: James W. Adkisson, Natalie B. Feilchenfeld, Jeffrey P. Gambino, Howard S. Landis, Benjamin T. Voegeli, Steven H. Voldman, Michael J. Zierak
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Patent number: 7868809Abstract: A resistor-based digital to analog converter (DAC) having mux fastpaths, which selectively connect a subset (or an entirety) of voltage divider nodes in a DAC to either a higher level of multiplexor hierarchy, or a DAC output node, effectively bypassing one or more levels of multiplexor devices. In addition, the fastpaths may selectively connect lower levels of multiplexor hierarchy to higher levels of multiplexor hierarchy and/or a DAC output node.Type: GrantFiled: February 20, 2009Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Joseph A. Iadanza, Benjamin T Voegeli
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Patent number: 7829945Abstract: A gate stack comprising a uniform thickness gate dielectric, a gate electrode, and an oxygen-diffusion-resistant gate cap is formed on a semiconductor substrate. Thermal oxidation is performed only on the drain side of the gate electrode, while the source side is protected from thermal oxidation. A thermal oxide on the drain side sidewall of the gate electrode is integrally formed with a graded thickness silicon oxide containing gate dielectric, of which the thickness monotonically increases from the source side to the drain side. The thickness profile may be self-aligned to the drain side edge of the gate electrode, or may have a portion with a self-limiting thickness. The graded thickness profile may be advantageously used to form a lateral diffusion metal oxide semiconductor field effect transistor providing an enhanced performance.Type: GrantFiled: October 26, 2007Date of Patent: November 9, 2010Assignee: International Business Machines CorporationInventors: James W. Adkisson, Natalie B. Feilchenfeld, Jeffrey P. Gambino, Benjamin T. Voegeli, Michael J. Zierak
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Patent number: 7732835Abstract: A P-N junction device and method of forming the same are disclosed. The P-N junction device may include a P-N diode, a PiN diode or a thyristor. The P-N junction device may have a monocrystalline or polycrystalline raised anode. In one embodiment, the P-N junction device results in a raised polycrystalline silicon germanium (SiGe) anode. In another embodiment, the P-N junction device includes a first terminal (anode) including a conductor layer positioned above an upper surface of a substrate and a remaining structure positioned in the substrate, the first terminal positioned over an opening in an isolation region; and a second terminal (cathode contact) positioned over the opening in the isolation region adjacent the first terminal. This latter embodiment reduces parasitic resistance and capacitance, and decreases the required size of a cathode implant area since the cathode contact is within the same STI opening as the anode.Type: GrantFiled: June 25, 2008Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: Benjamin T. Voegeli, Steven H. Voldman