Abstract: Disclosed is a multi-phase pulse width modulated voltage regulator and method in which transient voltage excursions or deviations that exceed the load line voltage by more than a pre-determined amount are detected by an ATR circuit and a correction signal is applied. The correction signal is in the form of asynchronous pulses and the number of such pulses is a function of the magnitude of the voltage excursion as determined by the number of thresholds that are exceeded. Also disclosed is an adaptive voltage positioning (AVP) circuit and method for early detection of a transient event by sensing voltage changes at the load and adjusting the target voltage with pre-determined current values prior to the time that ATR event changes in the current at the load are detected.

Abstract: Reduction of administrative overhead in maintaining network information, rapid convergence on an optimal routing path through the data network, and utilization of only required network resources are realized by a novel method for establishing a call path between network users. The method is based upon deployment of a network information server that stores network topology information and that is addressable by each end user. In this method, the network information server receives a request to establish a call path. The request identifies at least the calling party. In response to the request, the network information server determines a network traversal between the calling party and a root network wherein the network traversal includes call path information about the sub-networks between the calling party and the root network. The request for establishing a call path can also identify the called party.

Abstract: A method, apparatus, and system for routing signals in a microelectronic device are disclosed. The system includes a plurality of chip components, such as transient suppression regulators, that are configured to include a transmission path that is routed through the chip component for transmission of any signal, for example, a signal from a communication bus of the microelectronic device.

Abstract: A serial bus control method, apparatus, and system for transmitting signals between a master controller and a slave controller associated with a power regulator are disclosed. The serial bus control scheme allows for information to be written to or read from individual regulators or be written to read from all regulators that are coupled to the master controller.

Abstract: A cross-point switch fabric slice (100) includes multistage gated buffer tree (135) incorporating at least first and second serially connected gated buffer stages (136, 138). N inputs (102-116) connect to preselected gated buffers (146-160) in the first gated buffer stage (136). The multistage gated buffer tree provides a signal path from any of the N inputs (102-116) to at least one switch output (118) in response to gated buffer stage control signals for the first gated buffer stage (136) and gated buffer stage control signals for the second gated buffer stage (138). Generally, the number of gated buffers decreases from that of the previous stage. As an input signal propagates through the cross-point switch fabric slice (100), longer internal connections are driven by more capable buffers.

Abstract: An apparatus and method for detecting the presence of a valid signal includes an offset generator coupled to a pair of data slicers and an XOR gate. The offset generator is configured to both add and subtract a predetermined voltage to an input voltage in its two outputs. The two outputs of the offset generator are both compared to a predetermined value in a pair of data slicers. If the outputs of the data slicers are the same (i.e., either both offset signals are positive or both are negative), then a valid signal is indicated.

Abstract: A sense circuit and a system including a sense circuit are disclosed. The sense circuit is configured to measure and change in current with respect to time and/or a change in voltage across a portion of a substrate.

Abstract: The present invention is directed to an improved system and method for transmitting and receiving digital data. In order to counter the spatial filtering effects of a digital data bus, data is spatially filtered by a driver before being sent on the digital data bus to its destination. In the alternative, the data may be spatially filtered by a receiver after being sent on the digital data bus. The spatial filter may include one or more current-limiting elements, such as a resistor or a transistor, coupled between the power supply and the various buffers on the bus. Such a configuration results in a lowering of the crosstalk and ground bounce present between adjacent lines on a data bus.

Abstract: The present invention includes a system and method for improving phase selection using a phase selector system. An exemplary phase selector system of the present invention includes a high speed phase selector having control logic, XOR gates, and a selector. The control logic uses Gray coding to generate one or more control signals. For example, the control logic uses a 3 bit word to select a phase for clock recovery. A selector coupled to the control logic determines the phase selected. XOR gates coupled between the control logic and the selector provide eight phases of a clock using four input phases of the clock with inversion. In this manner, a four to one selector can choose one of eight phases from the XOR gates to aid in clock recovery. The selector control logic has a continuous output phase during a change to an adjacent phase, which substantially prevents glitching on the clock.

Abstract: A parallel punctured convolutional encoder (44) that provides convolutional coding of a stream of digital data bits in a parallel manner for high frequency transmission. The parallel convolutional encoder (44) includes a plurality of one-bit delay devices (46-56) and four XOR gates (78-84). Three consecutive bits are applied to the convolutional encoder (44) in a parallel manner and four polynomial expressions are provided from the XOR gates 78-84 in a parallel manner at each clock cycle, where certain values in the polynomial expressions are provided and certain values are not provided to conform with a particular puncture scheme of a desirable convolutional rate. In an altnerate embodiment, a concatenated Reed-Solomon TCM QAM encoder is provided that operates on parallel lines of digital data for high frequency communications systems.

Abstract: The chip-to-board (or chip-to-MCM) connection assembly and method therefor features a semiconductor chip (31) having a front surface (31f) on which external terminal pads are provided; a board or MCM (32) having a surface (e.g., a recessed surface) at a first side thereof to which the rear surface (31r) of the chip is affixed; and a connection carrier (33), disposed as an overlay, which electrically links the chip and the board or MCM. In this assembly scheme, the connection carrier (e.g., a bump carrier) which is affixed to both the chip and the board or MCM, contains all required signal line tracings (57) to provide the electrical interconnection between the semiconductor chip and the board or MCM. The bump carrier replaces all bond wires (24) and the like and can include support/control circuitry, passive and/or active, associated with, for example, high-speed/high-power IC chips (51).