Patents by Inventor Benjamin Tsien
Benjamin Tsien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111442Abstract: Systems, apparatuses, and methods for prefetching data by a display controller. From time to time, a performance-state change of a memory are performed. During such changes, a memory clock frequency is changed for a memory subsystem storing frame buffer(s) used to drive pixels to a display device. During the performance-state change, memory accesses may be temporarily blocked. To sustain a desired quality of service for the display, a display controller is configured to prefetch data in advance of the performance-state change. In order to ensure the display controller has sufficient memory bandwidth to accomplish the prefetch, bandwidth reduction circuitry in clients of the system are configured to temporarily reduce memory bandwidth of corresponding clients.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Inventors: Ashish Jain, Shang Yang, Jun Lei, Gia Tung Phan, Oswin Hall, Benjamin Tsien, Narendra Kamat
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Patent number: 11947476Abstract: Methods and systems are disclosed for cross-chiplet performance data streaming. Techniques disclosed include accumulating, by a subservient chiplet, event data associated with an event indicative of a performance aspect of the subservient chiplet; sending, by the subservient chiplet, the event data over a chiplet bus to a master chiplet; and adding, by the master chiplet, the received event data to an event record, the event record containing previously received, from the subservient chiplet over the chiplet bus, event data associated with the event.Type: GrantFiled: March 31, 2022Date of Patent: April 2, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Bryan Broussard, Pravesh Gupta, Benjamin Tsien, Vydhyanathan Kalyanasundharam
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Publication number: 20240103754Abstract: Systems, apparatuses, and methods for prefetching data by a display controller. From time to time, a performance-state change of a memory are performed. During such changes, a memory clock frequency is changed for a memory subsystem storing frame buffer(s) used to drive pixels to a display device. During the performance-state change, memory accesses may be temporarily blocked. In order to reduce visual artifacts that may occur while the memory accesses are blocked, a memory subsystem includes a control circuit configured to enable a caching mode which caches display data provided to the display controller. Subsequent requests for display data from the display controller are then serviced using the cached data instead of accessing memory.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Inventors: Gia Tung Phan, Ashish Jain, Chintan S. Patel, Benjamin Tsien, Jun Lei, Shang Yang, Oswin Hall
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Patent number: 11940858Abstract: A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.Type: GrantFiled: October 25, 2022Date of Patent: March 26, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Amit P. Apte
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Patent number: 11899520Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.Type: GrantFiled: April 26, 2022Date of Patent: February 13, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Ashish Jain, Benjamin Tsien, Chintan S. Patel, Vydhyanathan Kalyanasundharam, Shang Yang
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Publication number: 20240004815Abstract: Systems and methods are disclosed for scheduling a data link training by a controller. The system and method include receiving an indication that a physical layer of a data link is not transferring data and initiating a training process of the physical layer of the data link in response to the indication that the physical layer of the data link is not transferring data. In one aspect, the indication that the physical layer of a data link is not transferring data is an indication that the physical layer of the data link is in a low power state. In another aspect, the indication that the physical layer of a data link is not transferring data is an indication that a data transfer has been completed.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Michael J. Tresidder, Benjamin Tsien
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Publication number: 20240004721Abstract: An apparatus and method for efficiently performing power management for a multi-client computing system. In various implementations, a computing system includes multiple clients that process tasks corresponding to applications. The clients store generated requests of a particular type while processing tasks. A client receives an indication specifying that another client is having requests of the particular type being serviced. In response to receiving this indication, the client inserts a first urgency level in one or more stored requests of the particular type prior to sending the requests for servicing. When the client determines a particular time interval has elapsed, the client sends an indication to other clients specifying that requests of the particular type are being serviced. The client also inserts a second urgency level different from the first urgency level in one or more stored requests of the particular type prior to sending the requests for servicing.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Inventors: Indrani Paul, Alexander J. Branover, Benjamin Tsien, Elliot H. Mednick
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Publication number: 20240004821Abstract: Systems and methods are disclosed for voltage droop mitigation associated with a voltage rail that supplies power to circuitry of a chiplet. Techniques disclosed include detecting an upcoming transmission of data packets that are to be transmitted through a physical layer of the chiplet. Then, before transmitting the data packets through the physical layer, throttling a rate of bandwidth utilization in the physical layer and transmitting, by the controller, the data packets through the physical layer.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Michael J. Tresidder, Benjamin Tsien
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Publication number: 20230418745Abstract: A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Chintan S. Patel, Vydhyanathan Kalyanasundharam, Benjamin Tsien, Alexander J. Branover
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Publication number: 20230418753Abstract: A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Chintan S. Patel, Alexander J. Branover, Benjamin Tsien, Edgar Munoz, Vydhyanathan Kalyanasundharam
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Publication number: 20230350484Abstract: A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component, and executes a process to exit the component from the reduced power state in response to the component being active.Type: ApplicationFiled: April 21, 2023Publication date: November 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Mihir Shaileshbhai Doctor, Alexander J. Branover, Benjamin Tsien, Indrani Paul, Christopher T. Weaver, Thomas J. Gibney, Stephen V. Kosonocky, John P. Petry
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Publication number: 20230341922Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.Type: ApplicationFiled: April 26, 2022Publication date: October 26, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Ashish Jain, Benjamin Tsien, Chintan S. Patel, Vydhyanathan Kalyanasundharam, Shang Yang
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Publication number: 20230315657Abstract: Methods and systems are disclosed for cross-chiplet performance data streaming. Techniques disclosed include accumulating, by a subservient chiplet, event data associated with an event indicative of a performance aspect of the subservient chiplet; sending, by the subservient chiplet, the event data over a chiplet bus to a master chiplet; and adding, by the master chiplet, the received event data to an event record, the event record containing previously received, from the subservient chiplet over the chiplet bus, event data associated with the event.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Bryan Broussard, Pravesh Gupta, Benjamin Tsien, Vydhyanathan Kalyanasundharam
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Publication number: 20230315188Abstract: Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Thomas J. Gibney, Mihir Shaileshbhai Doctor, Indrani Paul, Benjamin Tsien, Stephen V. Kosonocky, John P. Petry, Christopher T. Weaver
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Publication number: 20230280819Abstract: A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.Type: ApplicationFiled: May 12, 2023Publication date: September 7, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Alexander J. Branover, Christopher T. Weaver, Benjamin Tsien, Indrani Paul, Mihir Shaileshbhai Doctor, Thomas J. Gibney, John P. Petry, Dennis Au, Oswin Hall
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Patent number: 11734151Abstract: An integrated circuit (IC) includes a first circuit including a timer for receiving an adjustable clock signal. Responsive to leaving the non-operational power state to enter a power state in which the adjustable clock has a lower frequency than the reference clock, the first circuit adjusts the frequency of the adjustable clock to a frequency higher than the lower frequency, and then receives an elapsed time associated with the non-operational power state and starts the timer using an adjusted timer value.Type: GrantFiled: June 24, 2021Date of Patent: August 22, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Pravesh Gupta
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Patent number: 11703932Abstract: A data fabric routes requests between the plurality of requestors. A probe filter tracks the state of cached lines of memory at a probe filter coupled to the data fabric. Responsive to the data fabric leaving a non-operational power state while all requestors that are probe filter clients are in a non-operational power state, the power management controller delays a probe filter initialization state in which data regarding cached lines is initialized following the non-operational power state.Type: GrantFiled: June 24, 2021Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Amit P. Apte
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Patent number: 11703937Abstract: Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.Type: GrantFiled: September 23, 2021Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Mihir Shaileshbhai Doctor, Alexander J. Branover, Benjamin Tsien, Indrani Paul, Christopher T. Weaver, Thomas J. Gibney, Stephen V. Kosonocky, John P. Petry
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Publication number: 20230205297Abstract: A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.Type: ApplicationFiled: December 27, 2021Publication date: June 29, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Thomas J. Gibney, Stephen V. Kosonocky, Mihir Shaileshbhai Doctor, John P. Petry, Indrani Paul, Benjamin Tsien, Christopher T. Weaver
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Publication number: 20230195644Abstract: A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Chintan S. Patel, Guhan Krishnan, Andrew William Lueck, Sreenath Thangarajan