Abstract: A method, system, and apparatus determines whether a task should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. The task is relocated from the first processor to the second processor and executed on the second processor based on the com paring.

Abstract: A disclosed technique includes transmitting data in a first buffer associated with a first display pipe to a first display associated with the first display pipe; transmitting data in a second buffer associated with a second display pipe to the first display; requesting wake-up of a memory; and refilling one or both of the first buffer and the second buffer from the memory.

Abstract: A disclosed technique includes triggering a change for a first set of one or more functional elements and for a second set of one or more functional elements from a high-power state to a low-power state; saving first state of the first set of one or more functional elements via a first set of one or more save-state elements; saving second state of the second set of one or more functional elements via a second set of one or more save-state elements; powering down the first set of one or more functional elements and the second set of one or more functional elements; and transmitting the first state and the second state to a memory.

Abstract: A method and apparatus for isolating and restoring general-purpose input/output (GPIO) pads in a computer system includes identifying GPIO pads associated with the region responsive to an entry into a power-down state of a region of a circuit. The GPIO pads are isolated from one or more external circuits. Upon exit from the power-down state, each associated GPIO pad is restored to a current value.

Abstract: Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.

Abstract: A method and apparatus for managing a controller includes indicating, by a processor of a first device, to the controller of a second device to enter a second power state from a first power state. The controller of the second device responds to the processor of the first device with a confirmation. The processor of the first device transmits a signal to the controller of the second device to enter the second power state. Upon receiving a wake event, the controller of the second device exits the second device from the second power state to the first power state.

Abstract: Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.

Abstract: Devices and methods for cache prefetching are provided. A device is provided which comprises a quality of service (QOS) component having first assigned registers used to store data to execute a program, a plurality of non-QOS components having second assigned registers used to store data to execute the program and a power management controller, in communication with the QOS component and the non-QOS components. The power management controller is configured to issue fences for the non-QOS components when it is determined that one or more of the non-QOS components are idle, issue a fence for the QOS component when the fences for the non-QOS components are completed and enter a reduced power state when the fences for the non-QOS components and the fence for the QOS component are completed.

Abstract: A method, system, and apparatus determines that one or more tasks should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. To relocate the one or more tasks from the first processor to the second processor, the first processor is stalled and state information from the first processor is copied to the second processor. The second processor uses the state information and then services incoming tasks instead of the first processor.

Abstract: A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

Abstract: A data processor includes a plurality of requestors, a plurality of responders, and a data fabric. The data fabric is for routing requests between the plurality of requestors and the plurality of responders and has a plurality of non-operational power states including a normal C-state and a light-weight C-state. The light-weight C-state has lower entry and exit latencies than the normal C-state. The data fabric monitors traffic through the data fabric and places the data fabric in the light-weight C-state in response to detecting an idle traffic state.

Abstract: A disclosed technique includes triggering a change for a first set of one or more functional elements and for a second set of one or more functional elements from a high-power state to a low-power state; saving first state of the first set of one or more functional elements via a first set of one or more save-state elements; saving second state of the second set of one or more functional elements via a second set of one or more save-state elements; powering down the first set of one or more functional elements and the second set of one or more functional elements; and transmitting the first state and the second state to a memory.

Abstract: A disclosed technique includes transmitting data in a first buffer associated with a first display pipe to a first display associated with the first display pipe; transmitting data in a second buffer associated with a second display pipe to the first display; requesting wake-up of a memory; and refilling one or both of the first buffer and the second buffer from the memory.

Abstract: A disclosed technique includes triggering entry into a clock bypass mode, in which a bypass clock generator provides clock signals to functional elements and a primary clock generator does not provide clock signals to functional elements; and triggering exit from the clock bypass mode, in which the bypass clock generator does not provide clock signals to the functional elements and the primary clock generator does provide clock signals to the functional elements.

Abstract: Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.

Abstract: An integrated circuit (IC) includes a first circuit including a timer for receiving an adjustable clock signal. Responsive to leaving the non-operational power state to enter a power state in which the adjustable clock has a lower frequency than the reference clock, the first circuit adjusts the frequency of the adjustable clock to a frequency higher than the lower frequency, and then receives an elapsed time associated with the non-operational power state and starts the timer using an adjusted timer value.

Abstract: A data fabric routes requests between the plurality of requestors. A probe filter tracks the state of cached lines of memory at a probe filter coupled to the data fabric. Responsive to the data fabric leaving a non-operational power state while all requestors that are probe filter clients are in a non-operational power state, the power management controller delays a probe filter initialization state in which data regarding cached lines is initialized following the non-operational power state.

Abstract: A processor in a system is responsive to a coherent memory request buffer having a plurality of entries to store coherent memory requests from a client module and a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests from the client module. The client module buffers coherent and non-coherent memory requests and releases the memory requests based on one or more conditions of the processor or one of its caches. The memory requests are released to a central data fabric and into the system based on a first watermark associated with the coherent memory buffer and a second watermark associated with the non-coherent memory buffer.

Abstract: A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

Abstract: A method of controlling a cache is disclosed. The method comprises receiving a request to allocate a portion of memory to store data. The method also comprises directly mapping a portion of memory to an assigned contiguous portion of the cache memory when the request to allocate a portion of memory to store the data includes a cache residency request that the data continuously resides in cache memory. The method also comprises mapping the portion of memory to the cache memory using associative mapping when the request to allocate a portion of memory to store the data does not include a cache residency request that data continuously resides in the cache memory.