Patents by Inventor Benoit Nadeau-Dostie

Benoit Nadeau-Dostie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040163021
    Abstract: An improvement in a scan testing method for testing a circuit having memory elements arranged into one or more scan chains, the scan testing method having a shift phase for serially loading test patterns into the scan chains and serially unloading test response patterns from the scan chains and a capture phase for capturing the response of the circuit to the test pattern, comprises, during the capture phase, connecting the serial output of each scan chain to its serial input and applying a predetermined number of capture clock cycles with the memory elements configured in a non-capture mode for all but the last capture clock cycle and configured in capture mode for the last capture clock cycle.
    Type: Application
    Filed: December 19, 2003
    Publication date: August 19, 2004
    Inventor: Benoit Nadeau-Dostie
  • Patent number: 6763489
    Abstract: A method for at-speed scan testing of circuits having scannable memory elements which source multi-cycle paths having propagation delays that are longer than the period of a system clock used during normal operation comprises loading a test stimulus into the scannable memory elements; performing a capture operation, including configuring in capture mode throughout the capture operation, non-source memory elements and multi-cycle path source memory elements which have a predetermined maximum capture clock rate which is the same as or higher than the clock rate of the capture clock; and configuring in a hold mode during all but the last cycle of the capture operation and in capture mode for the last cycle, source memory elements which have a predetermined maximum capture clock rate which is lower than the clock rate of the capture clock; applying at least two clock cycles of the capture clock; and unloading test response data captured by said scannable memory elements.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: July 13, 2004
    Assignee: LogicVision, Inc.
    Inventors: Benoit Nadeau-Dostie, Jean-François Côté
  • Patent number: 6760874
    Abstract: A test access circuit (TAC) for use in controlling test resources including child test access circuits (TACs) and/or test controllers, in an integrated circuit, comprises an enable input for enabling or disabling access to the test resources, a test port associated with each test resource, each test port including a test port enable output for connection to an enable input of an associated test resource; and an input for receiving a serial output of the associated test resource; and a selector for selecting a test resource for communication therewith.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: July 6, 2004
    Assignee: LogicVision, Inc.
    Inventors: Jean-François Côté, Benoit Nadeau-Dostie
  • Publication number: 20040123203
    Abstract: A method of testing write enable lines of random access memory having at least one word having one or more write enable inputs for controlling write operations in the word, comprises, for a selected memory address, shifting a series of test bits through an addressed word via a first data input to the word, and for each test bit, performing a write operation to the word using a write enable test input derived from data outputs of the word or from a test write enable signal applied concurrently to each write enable input; and, after each write operation, comparing a last bit of the word against an expected value to determine whether there exists a defect in a write enable line.
    Type: Application
    Filed: August 12, 2003
    Publication date: June 24, 2004
    Inventors: Benoit Nadeau-Dostie, Saman M. I. Adham
  • Patent number: 6745359
    Abstract: A method of masking corrupt bits in test response pattern scan chains in an integrated circuit, comprising loading and applying a set of test patterns in the scan chains so as to obtain corresponding test response patterns; and masking bits of the test response patterns located in scan chains identified by a chain mask and at a position identified by a position mask.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: June 1, 2004
    Assignee: LogicVision, Inc.
    Inventor: Benoit Nadeau-Dostie
  • Publication number: 20040098648
    Abstract: A circuit and a method are provided for testing the enable function of Boundary Scan Register bits that control the driver of unconnected I/O pins of an 1149.1-compliant IC during the IC's reduced pin-count access manufacturing test, and to test the connections to these pins during the test of a circuit board containing the IC, without causing excessive current if a pin is inadvertently short circuited.
    Type: Application
    Filed: November 6, 2003
    Publication date: May 20, 2004
    Inventors: Stephen K. Sunter, Pierre Gauthier, Benoit Nadeau-Dostie
  • Patent number: 6738938
    Abstract: A method of collecting failure information when testing a memory comprises performing a test of the memory according to a test algorithm, and, while performing the test, counting failure events which occur after a predetermined number of masked events; stopping the test upon occurrence of a stopping criterion which comprises one of occurrence of a first failure event, a change of a test operation; a change of a memory column address; a change of a memory row address; a change of a memory bank address; and a change of a test algorithm phase; and storing failure information.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: May 18, 2004
    Assignee: LogicVision, Inc.
    Inventors: Benoit Nadeau-Dostie, Jean-François Côté
  • Publication number: 20040003329
    Abstract: A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern comprises performing a number of test operations and storing a test response signature corresponding to each block of test patterns into a signature register; replacing the test response signature in the signature register with a test block expected signature; identifying the block as a failing test block when the test response signature is different from the test block expected signature; and repeating preceding steps until the test is complete.
    Type: Application
    Filed: June 27, 2002
    Publication date: January 1, 2004
    Inventors: Jean-Francois Cote, Benoit Nadeau-Dostie
  • Patent number: 6671839
    Abstract: A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern comprises performing a number of test operations and storing a test response signature corresponding to each block of test patterns into a signature register; replacing the test response signature in the signature register with a test block expected signature; identifying the block as a failing test block when the test response signature is different from the test block expected signature; and repeating preceding steps until the test is complete.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: December 30, 2003
    Assignee: LogicVision, Inc.
    Inventors: Jean-François Côté, Benoit Nadeau-Dostie
  • Publication number: 20030229833
    Abstract: A method of masking corrupt bits in test response pattern scan chains in an integrated circuit, comprising loading and applying a set of test patterns in the scan chains so as to obtain corresponding test response patterns; and masking bits of the test response patterns located in scan chains identified by a chain mask and at a position identified by a position mask.
    Type: Application
    Filed: June 6, 2002
    Publication date: December 11, 2003
    Inventor: Benoit Nadeau-Dostie
  • Publication number: 20030226073
    Abstract: A method of collecting failure information when testing a memory comprises performing a test of the memory according to a test algorithm, and, while performing the test, counting failure events which occur after a predetermined number of masked events; stopping the test upon occurrence of a stopping criterion which comprises one of occurrence of a first failure event, a change of a test operation; a change of a memory column address; a change of a memory row address; a change of a memory bank address; and a change of a test algorithm phase; and storing failure information.
    Type: Application
    Filed: May 29, 2002
    Publication date: December 4, 2003
    Inventors: Benoit Nadeau-Dostie, Jean-Francois Cote
  • Publication number: 20030217315
    Abstract: A method of fault diagnosis of integrated circuits having failing test vectors with observed fault effects using fault candidate fault-effects obtained by simulation of a set of test vectors, comprises determining a fault candidate diagnostic measure for each fault candidate, the fault candidate diagnostic measure having a fault candidate match metric, an observed fault effect mismatch metric and a fault candidate excitation metric, ranking fault candidates in decreasing diagnostic measure order; and identifying fault candidate(s) having the highest diagnostic measure as the most likely cause of observed fault effects.
    Type: Application
    Filed: May 12, 2003
    Publication date: November 20, 2003
    Inventors: Fadi Maamari, Sonny Ngai San Shum, Benoit Nadeau-Dostie
  • Publication number: 20030212524
    Abstract: A test access circuit (TAC) for use in controlling test resources including child test access circuits (TACs) and/or test controllers, in an integrated circuit, comprises an enable input for enabling or disabling access to the test resources, a test port associated with each test resource, each test port including a test port enable output for connection to an enable input of an associated test resource; and an input for receiving a serial output of the associated test resource; and means for selecting a test resource for communication therewith.
    Type: Application
    Filed: May 7, 2002
    Publication date: November 13, 2003
    Inventors: Jean-Francois Cote, Benoit Nadeau-Dostie
  • Patent number: 6614263
    Abstract: One aspect of the invention is generally defined as a method of designing an integrated circuit for distributing test clock signals to embedded cores having at least one core functional clock input, the method comprising, for each core, providing a clock gating circuit for selectively disabling a core functional clock signal applied to a core primary clock input; and providing a core clock selection circuit for each secondary core functional clock input for selecting one of a core functional clock signal output by the gating circuit and a core test clock signal and applying a selected signal to the each secondary core functional clock input.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: September 2, 2003
    Assignee: LogicVision, Inc.
    Inventors: Benoit Nadeau-Dostie, Jean-Francois Côté
  • Patent number: 6615392
    Abstract: A method for use in the hierarchical design of integrated circuits having at least one module, each the module having functional memory elements and combinational logic, the method comprising reading in a description of the circuit; replacing the description of each functional memory element of the modules with a description of a scannable memory element configurable in scan mode and capture mode; partitioning each module into an internal partition and a peripheral partition by converting the description of selected scannable memory elements into a description of peripheral scannable memory elements which are configurable in an internal test mode, an external test mode and a normal operation mode; modifying the description of modules in the circuit description so as to arrange the memory elements into scan chains in which peripheral and internal scannable memory elements of each module are controlled by an associated module test controller when configured in internal test mode; and peripheral scannable memory
    Type: Grant
    Filed: July 27, 2000
    Date of Patent: September 2, 2003
    Assignee: Logicvision, Inc.
    Inventors: Benoit Nadeau-Dostie, Dwayne Burek, Jean-Francois Cote, Sonny Ngai San Shum, Pierre Girouard, Pierre Gauther, Sai Kennedy Vedantam, Luc Romain, Charles Bernard
  • Publication number: 20030146777
    Abstract: One aspect of the invention is generally defined as a method of designing an integrated circuit for distributing test clock signals to embedded cores having at least one core functional clock input, the method comprising, for each core, providing a clock gating circuit for selectively disabling a core functional clock signal applied to a core primary clock input; and providing a core clock selection circuit for each secondary core functional clock input for selecting one of a core functional clock signal output by the gating circuit and a core test clock signal and applying a selected signal to the each secondary core functional clock input.
    Type: Application
    Filed: April 19, 2002
    Publication date: August 7, 2003
    Inventors: Benoit Nadeau-Dostie, Jean-Francois Cote
  • Publication number: 20030115522
    Abstract: A method of designing a circuit having at least one hierarchical block which requires block specific test patterns to facilitate quiescent current testing of the circuit, comprises, for each block, configuring the block and any embedded blocks located one level down in design hierarchy in quiescent current test mode in which input and output peripheral memory elements are configured in internal test mode and in external test mode, respectively; generating quiescent current test patterns which do not result in elevated quiescent current levels and which include a bit for all memory elements in the block and for any peripheral memory elements in any embedded blocks located one level down in design hierarchy; and, if the block contains embedded blocks, synchronizing the test pattern with a corresponding test pattern generated for embedded blocks so that test patterns loaded in scan chains in the block are consistent with test patterns loaded in scan chains in said embedded blocks.
    Type: Application
    Filed: December 17, 2001
    Publication date: June 19, 2003
    Inventors: Benoit Nadeau-Dostie, Dwayne Burek
  • Publication number: 20030110457
    Abstract: A method of designing integrated circuits having an hierarchical structure for quiescent current testing, and the circuit which results therefrom is disclosed. The method comprises analyzing each of one or more selected hierarchical blocks independently of other selected blocks identify any circuit states of each block which could result in elevated quiescent current levels during quiescent current testing of the circuit, the analysis beginning with blocks at a lowest level of hierarchy and proceeding in sequence through each level of design hierarchy to a highest level of hierarchy containing a top-level block; and calculating a fault coverage for each selected block.
    Type: Application
    Filed: December 10, 2001
    Publication date: June 12, 2003
    Inventors: Benoit Nadeau-Dostie, Jean-Francois Cote
  • Patent number: 6536008
    Abstract: A number of fault injection circuits and corresponding methods for injecting correlated, uncorrelated, non-persistent and persisting faults at the primary outputs of boundary scan cells are disclosed. Fault data is loaded in the boundary scan cell update latch of all boundary scan cells at which a fault is to be injected. The fault injection circuits generate a fault inject signal which is applied to the control input of the standard cell output selector, an active signal causing the content of the update latch to be applied to the cell primary output. In order to provide for scan testing of the fault injection circuitry, the boundary scan cell shift and update latches and the fault flag latch (if employed) are provided with hold capability so that the contents of these elements can be controlled and their input captured in accordance with standard scan testing techniques.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: March 18, 2003
    Assignee: Logic Vision, Inc.
    Inventors: Benoit Nadeau-Dostie, Jean-François Cote, Pierre Gauthier
  • Patent number: 6510534
    Abstract: A method for at-speed testing high-performance digital systems and circuits having combinational logic and memory elements that may be both scannable and non-scannable is performed by enabling at least two clock pulses during a capture sequence following a shift sequence. The method provides for initialization of any non-scannable memory elements via the scannable memory elements at the beginning of the test before an at-speed test is performed. During initialization, control logic generates a signal to disable the generation of system clock pulses for capture. Instead, only one clock cycle derived from the test clock or a system clock is generated to initialize the non-scannable elements. The number of shift sequences required depends on the maximum number of non-scannable elements that must be traversed between two scannable memory elements. During the same initialization period, the output response analyzer is disabled since unknown data values will present in the stream of data shifted out.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: January 21, 2003
    Assignee: LogicVision, Inc.
    Inventors: Benoit Nadeau-Dostie, Fadi Maamari, Dwayne Burek, Jean-Francois Cote