Patents by Inventor Bernard Ginetti
Bernard Ginetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8890634Abstract: A modulator generates a baseband digital signal from an information-bearing digital signal. The baseband signal has time-varying phase and amplitude defined by a sequence of complex data words, each having an in-phase (I) component and a quadrature (Q) component. A noise-shaping modulator generates a noise-shaped digital signal from the baseband digital signal such that quantization noise in the noise-shaping modulator is attenuated by a spectral null of its noise transfer function. The spectral null is selected by a noise-shaping parameter corresponding to a selected one of a plurality of output frequencies. A signal converter generates an analog signal conveying the information of the information-bearing digital signal on an analog carrier signal having the selected output frequency.Type: GrantFiled: October 26, 2012Date of Patent: November 18, 2014Assignee: MStar Semiconductor, Inc.Inventors: Dennis Mahoney, Bernard Ginetti, Zhongxuan Zhang, Khurram Muhammad, Chih-Ming Hung, Ming-Yu Hsieh
-
Patent number: 8847803Abstract: Digital input words are received in parallel by a parallel digital-to-digital sigma-delta modulator. Error words corresponding to quantization error are added in parallel to the input words to form encoded data words. The encoded data words are quantized into parallel output words and the error words resulting from such quantization are distributed across parallel modulator stages to effect a predetermined quantization error spectral distribution. The quantized output words are output in parallel.Type: GrantFiled: May 30, 2012Date of Patent: September 30, 2014Assignee: MStar Semiconductor, Inc.Inventors: Zhongxuan Zhang, Bernard Ginetti
-
Patent number: 8781026Abstract: In one embodiment, a sequence of a plurality of pairs of in-phase (I) and quadrature (Q) modulated signal samples are applied to a radio frequency digital-to-analog converter (RFDAC) for upconversion. A phase of a local oscillator (LO) signal supplied to the RFDAC is selected according to a quadrant determined by signs of a given pair of I and Q modulated signal samples. The selected phase of the LO is supplied to the RFDAC for use in upconverting the sequence of I and Q modulated signal samples. In another embodiment, a current steering DAC is used for directly upconverting the I and Q modulated signal samples. A clock signal at four times the LO frequency is supplied to a counter and to the current steering DAC. One of the I and Q modulated signal samples and negative I and negative Q modulated signal samples is selected for supply to an input of the current steering DAC based on a count state of the counter.Type: GrantFiled: November 6, 2012Date of Patent: July 15, 2014Assignee: MStar Semiconductor, Inc.Inventors: Khurram Muhammad, Bernard Ginetti, Dennis Mahoney
-
Patent number: 8750413Abstract: An arbitrary modulation frequency of a modulating signal is selected. The modulating signal is applied to an information-bearing signal, where such modulation is carried out through digital signal processing operations. The digitally modulated signal is resolution-reduced and the quantization noise introduced by such is shaped to locate a spectral null in the noise transfer function of the resolution reducing modulator at the modulation frequency. Thus, the modulation frequency can be selected independently of the clock frequency at which the resolution-reduced samples are converted to an analog signal.Type: GrantFiled: May 31, 2012Date of Patent: June 10, 2014Assignee: MStar Semiconductor, Inc.Inventors: Bernard Ginetti, Zhongxuan Zhang
-
Publication number: 20140126671Abstract: In one embodiment, a sequence of a plurality of pairs of in-phase (I) and quadrature (Q) modulated signal samples are applied to a radio frequency digital-to-analog converter (RFDAC) for upconversion. A phase of a local oscillator (LO) signal supplied to the RFDAC is selected according to a quadrant determined by signs of a given pair of I and Q modulated signal samples. The selected phase of the LO is supplied to the RFDAC for use in upconverting the sequence of I and Q modulated signal samples. In another embodiment, a current steering DAC is used for directly upconverting the I and Q modulated signal samples. A clock signal at four times the LO frequency is supplied to a counter and to the current steering DAC. One of the I and Q modulated signal samples and negative I and negative Q modulated signal samples is selected for supply to an input of the current steering DAC based on a count state of the counter.Type: ApplicationFiled: November 6, 2012Publication date: May 8, 2014Applicant: MSTAR SEMICONDUCTOR, INC.Inventors: Khurram Muhammad, Bernard Ginetti, Dennis Mahoney
-
Publication number: 20140118081Abstract: A modulator generates a baseband digital signal from an information-bearing digital signal. The baseband signal has time-varying phase and amplitude defined by a sequence of complex data words, each having an in-phase (I) component and a quadrature (Q) component. A noise-shaping modulator generates a noise-shaped digital signal from the baseband digital signal such that quantization noise in the noise-shaping modulator is attenuated by a spectral null of its noise transfer function. The spectral null is selected by a noise-shaping parameter corresponding to a selected one of a plurality of output frequencies. A signal converter generates an analog signal conveying the information of the information-bearing digital signal on an analog carrier signal having the selected output frequency.Type: ApplicationFiled: October 26, 2012Publication date: May 1, 2014Applicant: MSTAR SEMICONDUCTOR, INC.Inventors: Dennis Mahoney, Bernard Ginetti, Zhongxuan Zhang, Khurram Muhammad, Chih-Ming Hung, Ming-Yu Hsieh
-
Patent number: 8610609Abstract: The present disclosure provides techniques for using an NMOS field effect transistor-based buffer to buffer a pair of complementary digital signals and output a pair of equivalently fast rising and fast falling complementary signals to simultaneously drive a differential pair of PMOS transistors of a unit cell that output an analog signal for a current steering DAC. Accordingly, a DAC comprises a latch circuit and a unit cell circuit. The latch circuit includes an NMOS field effect transistor-based buffer and is capable of receiving a first digital signal and a clock signal and outputting a second digital signal through the NMOS field effect transistor-based buffer according to the clock signal. The second digital signal is associated with the first digital signal. The unit cell circuit, coupled to the latch circuit, receives the second digital signal and outputs an analog signal representative of the first digital signal.Type: GrantFiled: March 16, 2012Date of Patent: December 17, 2013Assignee: MStar Semiconductor, Inc.Inventor: Bernard Ginetti
-
Publication number: 20130063293Abstract: Digital input words are received in parallel by a parallel digital-to-digital sigma-delta modulator. Error words corresponding to quantization error are added in parallel to the input words to form encoded data words. The encoded data words are quantized into parallel output words and the error words resulting from such quantization are distributed across parallel modulator stages to effect a predetermined quantization error spectral distribution. The quantized output words are output in parallel.Type: ApplicationFiled: May 30, 2012Publication date: March 14, 2013Applicant: MSTAR SEMICONDUCTOR, INC.Inventors: Zhongxuan Zhang, Bernard Ginetti
-
Publication number: 20130064324Abstract: An arbitrary modulation frequency of a modulating signal is selected. The modulating signal is applied to an information-bearing signal, where such modulation is carried out through digital signal processing operations. The digitally modulated signal is resolution-reduced and the quantization noise introduced by such is shaped to locate a spectral null in the noise transfer function of the resolution reducing modulator at the modulation frequency. Thus, the modulation frequency can be selected independently of the clock frequency at which the resolution-reduced samples are converted to an analog signal.Type: ApplicationFiled: May 31, 2012Publication date: March 14, 2013Applicant: MSTAR SEMICONDUCTOR, INC.Inventors: Bernard Ginetti, Zhongxuan Zhang
-
Publication number: 20130063292Abstract: The present disclosure provides techniques for using an NMOS field effect transistor-based buffer to buffer a pair of complementary digital signals and output a pair of equivalently fast rising and fast falling complementary signals to simultaneously drive a differential pair of PMOS transistors of a unit cell that output an analog signal for a current steering DAC. Accordingly, a DAC comprises a latch circuit and a unit cell circuit. The latch circuit includes an NMOS field effect transistor-based buffer and is capable of receiving a first digital signal and a clock signal and outputting a second digital signal through the NMOS field effect transistor-based buffer according to the clock signal. The second digital signal is associated with the first digital signal. The unit cell circuit, coupled to the latch circuit, receives the second digital signal and outputs an analog signal representative of the first digital signal.Type: ApplicationFiled: March 16, 2012Publication date: March 14, 2013Applicant: MSTAR SEMICONDUCTOR, INC.Inventor: Bernard Ginetti
-
Publication number: 20100321220Abstract: The present invention discloses a 1-bit cell circuit used in a pipelined analog to digital converter. The 1-bit cell circuit comprises a reference buffer for providing a reference voltage; a sample and charge transfer circuit for receiving an input signal to generate an output signal; and a dump circuit for dumping said reference voltage; wherein said reference buffer selectively connects to one of said sample and charge transfer circuit and said dump circuit according to said input signal.Type: ApplicationFiled: June 23, 2009Publication date: December 23, 2010Inventor: Bernard Ginetti
-
Patent number: 7852254Abstract: The present invention discloses a 1-bit cell circuit used in a pipelined analog to digital converter. The 1-bit cell circuit comprises a reference buffer for providing a reference voltage; a sample and charge transfer circuit for receiving an input signal to generate an output signal; and a dump circuit for dumping said reference voltage; wherein said reference buffer selectively connects to one of said sample and charge transfer circuit and said dump circuit according to said input signal.Type: GrantFiled: June 23, 2009Date of Patent: December 14, 2010Assignee: Mstar Semiconductor, Inc.Inventor: Bernard Ginetti
-
Patent number: 6737904Abstract: A method of producing a clock signal with reduced electromagnetic interference spectral components includes providing a first clock signal; producing a second clock signal by delaying the first clock signal; and generating a jittered clock signal by switching between the first clock signal and the second clock signal at times selected responsive to a random number generator.Type: GrantFiled: November 12, 1999Date of Patent: May 18, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Remi Butaud, Bernard Ginetti
-
Patent number: 6671870Abstract: A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. The automatic test pattern generation (ATPG) algorithm is operative to design and test an integrated circuit design.Type: GrantFiled: September 10, 2001Date of Patent: December 30, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Laurent Souef, Jerome Bombal, Bernard Ginetti
-
Publication number: 20020032898Abstract: A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. The automatic test pattern generation (ATPG) algorithm is operative to design and test an integrated circuit design.Type: ApplicationFiled: September 10, 2001Publication date: March 14, 2002Inventors: Laurent Souef, Jerome Bombal, Bernard Ginetti
-
Patent number: 6311318Abstract: A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. The automatic test pattern generation (ATPG) algorithm is operative to design and test an integrated circuit design.Type: GrantFiled: July 13, 1999Date of Patent: October 30, 2001Assignee: VLSI Technology, Inc.Inventors: Laurent Souef, Jerome Bombal, Bernard Ginetti
-
Patent number: 6202183Abstract: An improved system and method to ensure the testability of any analog cell embedded in a mixed signal IC is described wherein the testability is independent of the core logic of that IC, which does not require the dedication of any pin solely to the testing of that IC. A uniform analog test access port design simplifies chip layout, greatly reduces the nunber of MUXed pins required, and allows generation of an analog test program for the total chip which is a simple concatenation and re-use of the individual analog cell test programs.Type: GrantFiled: July 2, 1998Date of Patent: March 13, 2001Assignee: Philips Semiconductors Inc.Inventors: Bernard Ginetti, Christian Zotier, Olaf Granzow
-
Patent number: 6163289Abstract: A digital-to-analog converter with differential output voltage includes a resistor string with high and low reference voltages end nodes and with nodes located between adjacent resistors of the string, first switches of a first analog multiplexer for deriving first divided voltages from first nodes of the resistor string, second switches of a second analog multiplexer for deriving second divided voltages from second nodes of the resistor string, and a decoder device receiving a digital signal. The decoder device is coupled to the first switches for selecting the first switches according to a first code derived from a first bit portion of the digital signal, and the decoder device is coupled to the second switches for selecting the second switches according to a second code derived from a second bit portion of the digital signal different to the first bit portion, whereby a selected first divided voltage and a selected second divided voltage define a selected differential output voltage of the converter.Type: GrantFiled: September 23, 1998Date of Patent: December 19, 2000Assignee: Philips Electronics North America Corp.Inventor: Bernard Ginetti
-
Patent number: 5894280Abstract: A digital to analog converter (DAC) offset autocalibration system in a digital synthesizer integrated circuit. The present invention includes a DAC coupled to a filter. The input of the DAC accepts digital values for conversion to an analog signal. The output of the DAC is coupled to the input of the filter. The filter smoothes the analog signal received from the DAC. A switch is coupled to the filter output to receive the analog signal. A comparator is coupled to the switch. The input of the comparator receives the analog signal from the filter output via the switch. An autocalibration control circuit is coupled to the output of the comparator, to the switch, and to the DAC. The autocalibration control circuit is adapted to input a value to the DAC in order to determine an offset correction from the output of the comparator and adjust the analog signal using the offset correction.Type: GrantFiled: February 5, 1997Date of Patent: April 13, 1999Assignee: VLSI Technology, Inc.Inventors: Bernard Ginetti, Philippe Gaglione
-
Patent number: 5831566Abstract: A low voltage digital-to-analog converter (DAC) uses a resistor string to divide a supply voltage. The voltage output for the DAC is fixed at an intermediary node in the resistor string, and NMOS and PMOS transistors are used to switch in V.sub.SS and V.sub.DD respectively to nodes in the resistor string such that the NMOS and PMOS transistors are operated where they are most conductive. A decoder is used to decode the digital input to control the switches. One switch from each set of NMOS and PMOS transistors is activated for a given input, or thermometric decoding of the input is used to activate more than one switch from each set to preserve monotonicity. In an alternative embodiment, when matching of the resistors can be assumed, a two-step decoding process is used. An LSB decoder decodes the least significant bits of the digital input and controls how V.sub.DD is applied to a bank of LSB resistors through PMOS transistors, and how V.sub.Type: GrantFiled: May 7, 1996Date of Patent: November 3, 1998Assignee: VLSI Technology, Inc.Inventor: Bernard Ginetti