Abstract: An interstage amplifier for a pipelined analog-to-digital converter comprises an operational amplifier (50) having two balanced amplifying paths; a first pair of capacitors (55,58); a second pair of capacitors (56,57); and switching means (59-62) connected to the capacitors and said amplifier and arranged for: (i) during a first phase, enabling the first pair of capacitors (55,58) to receive a respective first sample of a first signal; (ii) during a second phase, enabling the second pair of capacitors (56,57) to receive a second sample of the first signal; (iii) during a third phase, enabling the first pair of capacitors (55,58) to receive a first sample of a second or reference signal and to enable charge to be transferred from each of the first pair of capacitors by way of a respective path of the amplifier to a respective one of the second pair of capacitors; and (iv) during a fourth phase, enabling the second pair of capacitors (56,57) to receive a second sample of the said second or reference signal and

Abstract: A digital-analog converter incorporates an array of current source cells connected at the output to a load as a function of an input code subdivided into H and V values, which are most significant bit (MSB) and least significant bit (LSB), respectively. The input code is converted into thermometric codes, respectively HT and VT, whose logic inverses are respectively horizontally and vertically routed to the array. Each position cell (h, v) in the array comprises a first and a second P type metal oxide semiconductor field effect transistor connected in series, and the series is in parallel with at least one third P type metal oxide semiconductor field effect transistor.

Abstract: An interstage amplifier for a pipelined analog to digital converter comprises an operational amplifier (50) having a first pair of capacitors (55,58), a second pair of capacitors (56,57), and switching means (59-62) connected to the capacitors and amplifier. The switching means interchanges the capacitor connections to compensate for offset in the amplifier. The arrangement provides first-order correction of capacitor mismatch.