Abstract: Described are methods and circuits that allow encrypted and unencrypted, or differently encrypted, configuration data to define the contents of the same physical memory frame or frames within a programmable logic device.

Abstract: Method and apparatus for a dynamically reconfigurable, including partially reconfigurable, multi-stage crossbar switch using configurable circuitry is described. Configurable circuitry is configured to provide the multi-stage crossbar switch with at least: a first stage configured from a first portion of the configurable circuitry to provide a first plurality of crossbars; a second stage configured from a second portion of the configurable circuitry to provide a second plurality of crossbars; and a third stage configured from a third portion of the configurable circuitry to provide a third plurality of crossbars. The first stage having inputs, and the third stage having outputs. The inputs and the outputs user selectable for responsive path configurable input-to-output cross-connectivity via the first stage, the second stage and the third stage using the first interconnects and the second interconnects.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: An FPGA includes a programmable interconnect structure in which the interconnect resources are divided into two groups. A first subset of the interconnect resources are optimized for high speed. A second subset of the interconnect resources are optimized for low power consumption. In some embodiments, the transistors of the first and second subsets have different threshold voltages. Transistors in the first subset, being optimized for speed, have a lower threshold voltage than transistors in the second subset, which are optimized for low power consumption. The difference in threshold voltages can be accomplished by using different doping levels, wells biased to different voltage levels, or using other well-known means. In some embodiments, the first subset of the interconnect resources includes buffers coupled to a higher voltage level than the second subset. In some embodiments, the first subset includes buffers manufactured using larger transistors than those in the second subset.

Abstract: Method and apparatus for designing custom programmable logic devices is described. In an example, a physical layout of programmable logic blocks is obtained. One or more dedicated logic blocks are then selected from a database. A physical size for each of the one or more dedicated logic blocks is obtained. A region within the physical layout for each of the one or more dedicated logic blocks is reserved in response to the respective physical size of each of the one or more dedicated logic blocks. Each or the one or more dedicated logic blocks is the positioned within the respective region reserved.

Abstract: A delay locked loop includes a primary delay line having a plurality of series-connected delay elements, wherein each of the delay elements operates in response to a supply voltage provided on a voltage supply line. When the delay locked loop is configured to operate in response to an input clock signal having a relatively high frequency, the voltage supply line is coupled to receive a first supply voltage. When the delay locked loop is configured to operate in response to an input clock signal having a relatively low frequency, the voltage supply line is coupled to receive a second supply voltage, which is significantly lower than the first supply voltage. When operating in response to the first supply voltage, the delay elements exhibit relatively short delays. Conversely, when operating in response to the second supply voltage, the delay elements exhibit relatively long delays.

Abstract: A general purpose interface tile of a first integrated circuit includes a plurality of micropads. A second integrated circuit may be stacked on the first integrated circuit such that signals from the second integrated circuit are communicated through the micropads and the interface tile to other circuitry on the first integrated circuit. Similarly, signals from the first integrated circuit are communicated through the interface tile and the micropads to the second integrated circuit. In the event that the first integrated circuit is a programmable logic device having a programmable interconnect structure, the interface tile is part of and hooks into the programmable interconnect structure and provides a general purpose mechanism for coupling signals from the second integrated circuit to the programmable interconnect structure and/or for coupling signals from the programmable interconnect structure to the second integrated circuit.

Abstract: Method and apparatus for communication within a programmable logic device using serial transceivers is described. In an example, an integrated circuit includes a first module and a second module. The first module and the second module each include a transceiver coupled to a serial/parallel interface, with each transceiver configured with at least one signal conductor for serial communication between the first module and the second module. The first module and the second module are configured to communicate with one another asynchronously. Each transceiver is configured to communicate with its respective serial/parallel interface in a synchronous time domain.

Abstract: An FPGA includes a programmable interconnect structure in which the interconnect resources are divided into two groups. A first subset of the interconnect resources are optimized for high speed. A second subset of the interconnect resources are optimized for low power consumption. In some embodiments, the transistors of the first and second subsets have different threshold voltages. Transistors in the first subset, being optimized for speed, have a lower threshold voltage than transistors in the second subset, which are optimized for low power consumption. The difference in threshold voltages can be accomplished by using different doping levels, wells biased to different voltage levels, or using other well-known means. In some embodiments, the first subset of the interconnect resources includes buffers coupled to a higher voltage level than the second subset. In some embodiments, the first subset includes buffers manufactured using larger transistors than those in the second subset.

Abstract: Method and apparatus for configuring a programmable logic device using configuration data stored in an external memory is described. In an example, a boundary scan port includes a data input terminal and a data output terminal. An instruction-set processor includes a first interface coupled to the boundary scan port and a second interface coupled to a configuration memory within the programmable logic device. The data output terminal of the boundary scan port is coupled to provide instruction data to the external memory and the data input terminal is coupled to receive configuration data from the external memory in response to the instruction data. The instruction-set processor is configured to provide configuration data to the configuration memory.

Abstract: An FPGA includes a programmable interconnect structure in which the interconnect resources are divided into two groups. A first subset of the interconnect resources are optimized for high speed. A second subset of the interconnect resources are optimized for low power consumption. In some embodiments, the transistors of the first and second subsets have different threshold voltages. Transistors in the first subset, being optimized for speed, have a lower threshold voltage than transistors in the second subset, which are optimized for low power consumption. The difference in threshold voltages can be accomplished by using different doping levels, wells biased to different voltage levels, or using other well-known means. In some embodiments, the first subset of the interconnect resources includes buffers coupled to a higher voltage level than the second subset. In some embodiments, the first subset includes buffers manufactured using larger transistors than those in the second subset.

Abstract: The circuitry of a programmable logic device (for example, an FPGA) includes a configurable logic portion and a configuration memory. The configuration memory stores configuration data that configures the configurable logic portion to realize a user-defined circuit. The configurable logic portion is disposed on a first die whereas the configuration memory is disposed on a second die. The second die is bonded to the first die in stacked relation. Each bit of configuration data passes from the second die to the first die through a pair of micropads. One micropad of the pair is disposed on the first die and the other micropad of the pair is disposed on the second die. When the first die and second die are brought together in face-to-face relation, the two micropads form an electrical connection through which the configuration data bit passes from the second die to the first die.

Abstract: The invention provides multi-chip modules (MCMs) that utilize transistors embedded in an active substrate to provide various desirable functions, optionally including programmable functions. In some embodiments, the MCM includes an active substrate having a field-programmable universal structure. The active substrate includes a regular grid pattern of lands separated by a programmable interconnect structure similar to those used in field programmable gate arrays (FPGAs). Interconnections within the programmable interconnect structure are controlled by values stored in configuration memory cells. The regular pattern of lands on the surface of the substrate permits the use of a single programmable active substrate to mount die of various sizes by means of solder bumps positioned to correspond to the land grid on the active substrate.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: A general purpose interface tile of a first integrated circuit includes a plurality of micropads. A second integrated circuit may be stacked on the first integrated circuit such that signals from the second integrated circuit are communicated through the micropads and the interface tile to other circuitry on the first integrated circuit. Similarly, signals from the first integrated circuit are communicated through the interface tile and the micropads to the second integrated circuit. In the event that the first integrated circuit is a programmable logic device having a programmable interconnect structure, the interface tile is part of and hooks into the programmable interconnect structure and provides a general purpose mechanism for coupling signals from the second integrated circuit to the programmable interconnect structure and/or for coupling signals from the programmable interconnect structure to the second integrated circuit.

Abstract: The circuitry of a programmable logic device (for example, an FPGA) includes a configurable logic portion and a configuration memory. The configuration memory stores configuration data that configures the configurable logic portion to realize a user-defined circuit. The configurable logic portion is disposed on a first die whereas the configuration memory is disposed on a second die. The second die is bonded to the first die in stacked relation. Each bit of configuration data passes from the second die to the first die through a pair of micropads. One micropad of the pair is disposed on the first die and the other micropad of the pair is disposed on the second die. When the first die and second die are brought together in face-to-face relation, the two micropads form an electrical connection through which the configuration data bit passes from the second die to the first die.

Abstract: An FPGA includes a programmable interconnect structure in which the interconnect resources are divided into two groups. A first subset of the interconnect resources are optimized for high speed. A second subset of the interconnect resources are optimized for low power consumption. In some embodiments, the transistors of the first and second subsets have different threshold voltages. Transistors in the first subset, being optimized for speed, have a lower threshold voltage than transistors in the second subset, which are optimized for low power consumption. The difference in threshold voltages can be accomplished by using different doping levels, wells biased to different voltage levels, or using other well-known means. In some embodiments, the first subset of the interconnect resources includes buffers coupled to a higher voltage level than the second subset. In some embodiments, the first subset includes buffers manufactured using larger transistors than those in the second subset.

Abstract: A method and apparatus to accelerate the evaluation of complex, computationally intense digital signal processing algorithms is disclosed. In one embodiment, a filter accelerator is connected in parallel with a conventional digital signal processor (DSP). The accelerator enhances the speed at which the DSP performs some filtering operations by calculating and maintaining a number of partial results based on a selected number of prior data samples. Each time the DSP receives a new data sample for filtering, the DSP makes use of one or more partial results from the accelerator to speed the calculation of the filtered result. Receipt of the new data sample causes the accelerator to recalculate the partial results, this time using the new data sample. The accelerator thus prepares for receipt of the subsequent data sample, freeing the DSP to perform other operations.

Abstract: A clock distribution circuit and method in which the incoming clock frequency is divided by two to create a reduced-frequency global clock signal. A dual-edge-correcting clock synchronization circuit aligns both the rising and falling edges of the global clock signal to separately to nullify the clock-distribution errors associated with rising and falling clock edges.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.