Abstract: A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, where current data to be written to a nonvolatile memory corresponds to an address cache hit is determined. If the current data to be written corresponds to an address cache hit, the current data are written to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to an address cache miss, the current data are written to the destined location in the nonvolatile memory. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.

Abstract: A method and apparatus managing online transaction using a computer system are disclosed. According to the present invention, a target request is received by a CPU coupled to a main memory and a memory application co-processor via a memory bus. The CPU then stores the target request onto the memory application co-processor coupled to a storage class memory. The memory application co-processor then locates target contents, inside the storage class memory, where the target key-word is specified in the target request. The CPU or a coupled device then accesses the target contents associated with the target key-word inside the storage class memory directly without copying the target contents associated with the target key-word inside the storage class memory to or from the main memory.

Abstract: A method and apparatus for read wearing control for storage class memory (SCM) are disclosed. The read data control apparatus, located between a host and the SCM subsystem, comprises a read data cache, an address cache and an SCM controller. The address cache stores pointers pointing to data stored in logging area(s) located in the SCM. For a read request, the read wearing control determines whether the read request is a read data cache hit, an address cache hit or neither (i.e., read data cache miss and address cache miss). For the read data cache hit, the requested data is returned from the read data cache. For the address cache hit, the requested data is returned from the logging area(s) and the read data becomes a candidate to be placed in the read data cache. For read data cache and address cache misses, the requested data is returned from SCM.

Abstract: A method and apparatus for read wearing control for storage class memory (SCM) are disclosed. The read data control apparatus, located between a host and the SCM subsystem, comprises a read data cache, an address cache and an SCM controller. The address cache stores pointers pointing to data stored in logging area(s) located in the SCM. For a read request, the read wearing control determines whether the read request is a read data cache hit, an address cache hit or neither (i.e., read data cache miss and address cache miss). For the read data cache hit, the requested data is returned from the read data cache. For the address cache hit, the requested data is returned from the logging area(s) and the read data becomes a candidate to be placed in the read data cache. For read data cache and address cache misses, the requested data is returned from SCM.

Abstract: A method and apparatus of bad location management for storage class memory are disclosed. A nonvolatile memory is partitioned into a non-reserved space and a reserved space, which are divided into multiple data units. The health status of the data units in the non-reserved space are classified into multiple classes including a mostly-good class. For host data read, the data from a mostly-good data unit are read and whether the data includes a pointer is checked. If no pointer, the data read are returned as the host data. Otherwise, the data unit pointed by the pointer is read. For data write, the data from a mostly-good data unit are read. If no pointer in the read data, the host data are written into the mostly-good data unit. Otherwise, the host data are written into the data unit in the reserved space pointed by the pointer.

Abstract: A method and apparatus of bad location management for storage class memory are disclosed. A nonvolatile memory is partitioned into a non-reserved space and a reserved space, which are divided into multiple data units. The health status of the data units in the non-reserved space are classified into multiple classes including a mostly-good class. For host data read, the data from a mostly-good data unit are read and whether the data includes a pointer is checked. If no pointer, the data read are returned as the host data. Otherwise, the data unit pointed by the pointer is read. For data write, the data from a mostly-good data unit are read. If no pointer in the read data, the host data are written into the mostly-good data unit. Otherwise, the host data are written into the data unit in the reserved space pointed by the pointer.

Abstract: An emergency mode is provided in a portable electronic device for locating a survivor in a disaster. The device includes a wireless antenna to transmit and receive wireless signals; a memory to store one or more identifiers; a user interface to receive a command that enables the emergency mode. The device also includes one or more processors, which, in response to the command, detect via the wireless receiver a predetermined identifier that matches a stored identifier identifying a sender of the predetermined identifier as a trusted node. When the predetermined identifier and a timing measurement frame are received from the trusted node, the device sends a response to the trusted node to indicate its presence.

Abstract: A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.

Abstract: A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.

Abstract: A processing device includes a first memory interface for accessing a first memory device of a main memory. Each first memory interface is compatible with Low-Power Double-Data-Rate (LPDDR) signaling. The processing device further includes a second memory interface, which has different signaling characteristics from the first memory interface, for accessing a second memory device of the main memory. The second memory device has an access latency higher than the first memory device and lower than a secondary storage device. The first memory device and the second memory device may be used as a dual memory or a two-tiered memory.

Abstract: A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.

Abstract: A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.

Abstract: A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, where current data to be written to a nonvolatile memory corresponds to an address cache hit is determined. If the current data to be written corresponds to an address cache hit, the current data are written to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to an address cache miss, the current data are written to the destined location in the nonvolatile memory. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.

Abstract: A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.

Abstract: A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.

Abstract: An emergency mode is provided in a portable electronic device for locating a survivor in a disaster. The device includes a wireless antenna to transmit and receive wireless signals; a memory to store one or more identifiers; a user interface to receive a command that enables the emergency mode. The device also includes one or more processors, which, in response to the command, detect via the wireless receiver a predetermined identifier that matches a stored identifier identifying a sender of the predetermined identifier as a trusted node. When the predetermined identifier and a timing measurement frame are received from the trusted node, the device sends a response to the trusted node to indicate its presence.

Abstract: A processing device includes a first memory interface for accessing a first memory device of a main memory. Each first memory interface is compatible with Low-Power Double-Data-Rate (LPDDR) signaling. The processing device further includes a second memory interface, which has different signaling characteristics from the first memory interface, for accessing a second memory device of the main memory. The second memory device has an access latency higher than the first memory device and lower than a secondary storage device. The first memory device and the second memory device may be used as a dual memory or a two-tiered memory.

Abstract: A wireless content protection system includes a coordinator, a source device, and a sink device. The coordinator includes a scheduler. The source and sink devices each have a content protection manager. One of the content protection manager allocates and releases bandwidth via the coordinator for a test message and a response message for a round-trip time computation. The test message is transmitted in a source-to-sink channel time block. The response message is transmitted in a sink-to-source channel time block. The round-trip time is the period between the end of the source-to-sink channel time block and the beginning of the sink-to-source channel time block.

Abstract: A wireless content protection system includes a coordinator, a source device, and a sink device. The coordinator includes a scheduler. The source and sink devices each have a content protection manager. One of the content protection manager allocates and releases bandwidth via the coordinator for a test message and a response message for a round-trip time computation. The test message is transmitted in a source-to-sink channel time block. The response message is transmitted in a sink-to-source channel time block. The round-trip time is the period between the end of the source-to-sink channel time block and the beginning of the sink-to-source channel time block.

Abstract: A shared buffer packet switching device is provided for receiving data packets via associated ones of a plurality of receive ports, and for transmitting data packets via associated selected ones of a plurality of transmit port.