Patents by Inventor Bernard V. Brezzo

Bernard V. Brezzo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10810487
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Patent number: 10628732
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20190228289
    Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
  • Patent number: 10331998
    Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
  • Patent number: 9818058
    Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20160358067
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Application
    Filed: August 22, 2016
    Publication date: December 8, 2016
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20160292569
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Application
    Filed: June 14, 2016
    Publication date: October 6, 2016
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Patent number: 9460383
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: October 4, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20160260008
    Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.
    Type: Application
    Filed: May 13, 2016
    Publication date: September 8, 2016
    Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20160247063
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Application
    Filed: September 2, 2014
    Publication date: August 25, 2016
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-Sun Seo, Jose A. Tierno
  • Patent number: 9373073
    Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 21, 2016
    Assignee: International Business Machines Corporation
    Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20160110640
    Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.
    Type: Application
    Filed: December 8, 2015
    Publication date: April 21, 2016
    Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
  • Patent number: 9239984
    Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: January 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
  • Patent number: 8983992
    Abstract: Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sameh Asaad, Bernard V. Brezzo, Donna N Eng Dillenberger, Parijat Dube, Balakrishna Raghavendra Iyer, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
  • Patent number: 8977637
    Abstract: Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sameh Asaad, Bernard V. Brezzo, Donna N Eng Dillenberger, Parijat Dube, Balakrishna Raghavendra Iyer, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
  • Patent number: 8898097
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Patent number: 8856055
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20140180987
    Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20140180984
    Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
  • Patent number: 8737233
    Abstract: Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sameh Asaad, Bernard V. Brezzo, Mohit Kapur