Abstract: Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.

Abstract: Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.

Abstract: Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.

Abstract: Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.

Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.