Abstract: Example embodiments relate to active-passive waveguide photonic systems. An example embodiment includes a monolithic integrated active/passive waveguide photonic system. The system includes a substrate having positioned thereon at least one active waveguide and at least one passive waveguide. The at least one active waveguide and the at least one passive waveguide are monolithically integrated and are arranged for evanescent wave coupling between the waveguides. The at least one active waveguide and the at least one passive waveguide are positioned so that at least a portion of each waveguide does not overlap the other waveguide, both in a height direction and in a lateral direction with respect to the substrate.

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.

Abstract: The disclosed technology generally relates to manufacturing of semiconductor devices, and more particularly to manufacturing of a semiconductor device by transferring an active layer from a donor substrate. One aspect is a method of manufacturing a semiconductor device includes providing a donor wafer for transferring an active layer, comprising a group IV, a group III-IV or a group II-VI semiconductor material, to a handling wafer. The method includes forming the active layer on a sacrificial layer of the donor wafer, bonding the donor wafer to the handling wafer, and selectively etching the sacrificial layer to remove the donor wafer from the handling wafer, thereby leaving the active layer on the handling wafer.

Abstract: Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.

Abstract: A monolithic integrated semiconductor structure includes: A) an Si carrier layer, B) a layer having the composition BxAlyGazNtPv, wherein x=0-0.1, y=0-1, z=0-1, t=0-0.1 and v=0.9-1, C) a relaxation layer having the composition BxAlyGazInuPvSbw, wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1 and w=0-1, wherein w and/or u is on the side facing toward layer A) or B) smaller than, equal to, or bigger than on the side facing away from layer A) or B) and wherein v=1?w and/or y=1?u?x?z, and D) a group III/V, semiconductor material. The sum of the above stoichiometric indices for all group III elements and for all group V elements are each equal to one.

Abstract: The present disclosure relates to a semiconductor structure and a method of preparation including a silicon monocrystalline substrate, and a III-V structure abutting the silicon monocrystalline substrate. The semiconductor structure includes an InaGabAs structure overlaying the III-V structure, where a is from 0.40 to 1, b from 0 to 0.60, and a+b equal to 1.00. The III-V structure has a top surface facing away from the silicon substrate. The top surface is GagXxPpSbsZz, where X includes one or more group III elements other than Ga and Z is one or more group V elements other than P or Sb. g is from 0.80 to 1.00, x is from 0 to 0.20, z is from 0 to 0.30, p is from 0.10 to 0.55, and s is from 0.50 to 0.80, g+x is equal to 1.00 and p+s+z is equal to 1.00.

Abstract: A method for producing a monolithic template comprises a Si wafer with a layer of a III/V semiconductor epitaxially applied to its surface. The III/V semiconductor has a lattice constant differing by less than 10% from that of Si. The method includes epitaxially growing a layer of a III/V semiconductor on the surface of the Si wafer at a wafer temperature from 350 to 650° C., a growth rate from 0.1 to 2 ?m/h, and a layer thickness from 1 to 100 nm. A layer of another III/V semiconductor, identical to or different from the previously applied III/V semiconductor, is epitaxially grown on the III/V semiconductor layer at a wafer temperature from 500 to 800° C., a growth rate from 0.1 to 10 ?m/h, and a layer thickness from 10 to 150 nm.

Abstract: The present disclosure relates to a semiconductor structure and a method of preparation including a silicon monocrystalline substrate, and a III-V structure abutting the silicon monocrystalline substrate. The semiconductor structure includes an InaGabAs structure overlaying the III-V structure, where a is from 0.40 to 1, b from 0 to 0.60, and a+b equal to 1.00. The III-V structure has a top surface facing away from the silicon substrate. The top surface is GagXxPpSbsZz, where X includes one or more group III elements other than Ga and Z is one or more group V elements other than P or Sb. g is from 0.80 to 1.00, x is from 0 to 0.20, z is from 0 to 0.30, p is from 0.10 to 0.55, and s is from 0.50 to 0.80, g+x is equal to 1.00 and p+s+z is equal to 1.00.

Abstract: Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.

Abstract: A monolithic integrated semiconductor structure includes: A) an Si carrier layer, B) a layer having the composition BxAlyGazNtPv, wherein x=0-0.1, y=0-1, z=0-1, t=0-0.1 and v=0.9-1, C) a relaxation layer having the composition BxAlyGazInuPvSbw, wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1 and w=0-1, wherein w and/or u is on the side facing toward layer A) or B) smaller than, equal to, or bigger than on the side facing away from layer A) or B) and wherein v=1?w and/or y=1?u?x?z, and D) a group III/V, semiconductor material. The sum of the above stoichiometric indices for all group III elements and for all group V elements are each equal to one.

Abstract: A monolithic integrated semiconductor structure includes: A) an Si carrier layer, B) a layer having the composition BxAlyGazNtPv, wherein x=0?0.1, y=0?1, z=0?1, t=0?0.1 and v=0.9?1, C) a relaxation layer having the composition BxAlyGazInuPvSbw, wherein x=0?0.1, y=0?1, z=0?1, u=0?1, v=0?1 and w=0?1, wherein w and/or u is on the side facing toward layer A) or B) smaller than, equal to, or bigger than on the side facing away from layer A) or B) and wherein v=1?w and/or y=1?u?x?z, and D) a group III/V, semiconductor material. The sum of the above stoichiometric indices for all group III elements and for all group V elements are each equal to one.

Abstract: The invention relates to a monolithic integrated semiconductor structure comprising a carrier layer on the basis of doped Si or doped GaP and a III/V semiconductor disposed thereupon and having the composition GaxInyNaAsbPcSbd, wherein x=70-100 mole-%, y=0-30 mole-%, a=0.5-15 mole-%, b=67.5-99.5 mole-%, c=0-32.0 mole-% and d=0-15 mole-%, wherein the total of x and y is always 100 mole-%, wherein the total of a, b, c and d is always 100 mole-%, and wherein the ratio of the totals of x and y on the one hand, and of a to d on the other hand, is substantially 1:1, to methods for the production thereof, new semiconductors, the use thereof for the production of luminescence diodes and laser diodes or also modulator and detector structures, which are monolithically integrated in integrated circuits on the basis of the Si or GaP technology.

Abstract: A method for producing a monolithic template comprises a Si wafer with a layer of a III/V semiconductor epitaxially applied to its surface. The III/V semiconductor has a lattice constant differing by less than 10% from that of Si. The method includes epitaxially growing a layer of a III/V semiconductor on the surface of the Si wafer at a wafer temperature from 350 to 650° C., a growth rate from 0.1 to 2 ?m/h, and a layer thickness from 1 to 100 nm. A layer of another III/V semiconductor, identical to or different from the previously applied III/V semiconductor, is epitaxially grown on the III/V semiconductor layer at a wafer temperature from 500 to 800° C., a growth rate from 0.1 to 10 ?m/h, and a layer thickness from 10 to 150 nm.

Abstract: A monolithic integrated semiconductor structure includes: A) an Si carrier layer, B) a layer having the composition BxAlyGazNtPv, wherein x=0?0.1, y=0?1, z=0?1, t=0?0.1 and v=0.9?1, C) a relaxation layer having the composition BxAlyGazInuPvSbw, wherein x=0?0.1, y=0?1, z=0?1, u=0?1, v=0?1 and w=0?1, wherein w and/or u is on the side facing toward layer A) or B) smaller than, equal to, or bigger than on the side facing away from layer A) or B) and wherein v=1?w and/or y=1?u?x?z, and D) a group III/V, semiconductor material. The sum of the above stoichiometric indices for all group III elements and for all group V elements are each equal to one.

Abstract: The invention relates to a monolithic integrated semiconductor structure comprising a carrier layer on the basis of doped Si or doped GaP and a III/V semiconductor disposed thereupon and having the composition GaxInyNaAsbPcSbd, wherein x=70-100 mole-%, y=0-30 mole-%, a=0.5-15 mole-%, b=67.5-99.5 mole-%, c=0-32.0 mole-% and d=0-15 mole-%, wherein the total of x and y is always 100 mole-%, wherein the total of a, b, c and d is always 100 mole-%, and wherein the ratio of the totals of x and y on the one hand, and of a to d on the other hand, is substantially 1:1, to methods for the production thereof, new semiconductors, the use thereof for the production of luminescence diodes and laser diodes or also modulator and detector structures, which are monolithically integrated in integrated circuits on the basis of the Si or GaP technology.

Abstract: The invention relates to a monolithic integrated semiconductor structure comprising a carrier layer on the basis of doped Si or doped GaP and a III/V semiconductor disposed thereupon and having the composition GaxInyNaAsbPcSbd, wherein x=70-100 mole-%, y=0-30 mole-%, a=0.5-15 mole-%, b=67.5-99.5 mole-%, c=0-32.0 mole-% and d=0-15 mole-%, wherein the total of x and y is always 100 mole-%, wherein the total of a, b, c and d is always 100 mole-%, and wherein the ratio of the totals of x and y on the one hand and of a to d on the other hand is substantially 1:1, to methods for the production thereof, new semiconductors, the use thereof for the production of luminescence diodes and laser diodes or also modulator and detector structures, which are monolithically integrated in integrated circuits on the basis of the Si or GaP technology.