Abstract: A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.

Abstract: The method comprises fabricating a semiconductor panel comprising a plurality of semiconductor devices, fabricating a cap panel comprising a plurality of caps, bonding the cap panel onto the semiconductor panel so that each one of the caps covers one or more of the semiconductor devices, and singulating the bonded panels into a plurality of semiconductor modules.

Abstract: A package comprising a chip carrier, an electronic chip on the chip carrier, a clip on the electronic chip, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive vertical connection structure provided separately from the clip and electrically connecting the chip carrier with the clip.

Abstract: Embodiments of the present disclosure provide an apparatus for determining a characteristic of a fluid. The apparatus may include a device configured to determine a hydrodynamic pressure of the fluid. The apparatus may further include a sensor configured to determine a hydrostatic pressure of the fluid or at least one component of the fluid. The apparatus may also include a common substrate on which the sensor and the device configured to determine a hydrodynamic pressure of the fluid may be commonly arranged, and an ASIC (Application Specific Integrated Circuit) which may be electrically coupled with at least one of the device or the sensor. The ASIC may be at least partially embedded in the common substrate.

Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.

Abstract: A method of fabricating a semiconductor package. In one embodiment the method includes forming a mold cavity about a portion of a first major surface of a leadframe, including about a mold lock opening extending through the leadframe between the first major surface and a second major surface. A spacer is inserted to fill at least a portion of the mold lock opening. The mold cavity is filled with an encapsulating material including filling a portion of the mold lock opening not occupied by the spacer.

Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.

Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.

Abstract: An electronic component has a first semiconductor chip and a second semiconductor chip that is arranged on a plastic compound in which the first semiconductor chip is embedded. The semiconductor chips are connected to one another by rewiring layers and vias which extend between the rewiring layers, the vias being widened at a transition to one of the rewiring layers.

Abstract: A method of fabricating a semiconductor package. In one embodiment the method includes forming a mold cavity about a portion of a first major surface of a leadframe, including about a mold lock opening extending through the leadframe between the first major surface and a second major surface. A spacer is inserted to fill at least a portion of the mold lock opening. The mold cavity is filled with an encapsulating material including filling a portion of the mold lock opening not occupied by the spacer.

Abstract: A leadframe for supporting a semiconductor chip, the leadframe including a die pad having a first major surface and an opposing second major surface defining a thickness and having at least one perimeter edge, and an opening spaced from the at least one perimeter edge and extending through the thickness of the die pad between the first and second major surfaces. A vent extends from the at least one perimeter edge to the opening so that the opening is in communication with the at least one perimeter edge.

Abstract: A semiconductor package including a leadframe having first and second major surfaces and a mold lock opening extending between the first and second major surfaces. The semiconductor package includes a semiconductor die coupled to the first major surface, and an encapsulating material formed about the semiconductor chip and a portion of the first major surface of the leadframe and filling all but a portion of the mold lock opening, the unfilled portion of the mold lock opening forming a vent extending from the second major surface to the first major surface, the vent providing a pathway for air to escape from between the second major surface and a surface to which the second major surface is to be attached.

Abstract: A semiconductor wafer, a panel, and an electronic component, and also methods for producing them is disclosed. In this context, the electronic component has a stack of two semiconductor chips. The top stacked semiconductor chip is thin-ground and is arranged using flip-chip technology on a central region of the bottom semiconductor chip. An edge region of the bottom semiconductor chip contains vias through a leveling layer to a rewiring plane, which for its part carries external contacts.

Abstract: A sensor component and a panel used for the production thereof is disclosed. The sensor component has, in addition to a sensor chip with a sensor region, a rear side and passive components. These are embedded jointly in a plastics composition, in such a way that their respective electrodes can be wired from an overall top side of a plastic plate.

Abstract: A semiconductor package including a leadframe having first and second major surfaces and a mold lock opening extending between the first and second major surfaces. The semiconductor package includes a semiconductor die coupled to the first major surface, and an encapsulating material formed about the semiconductor chip and a portion of the first major surface of the leadframe and filling all but a portion of the mold lock opening, the unfilled portion of the mold lock opening forming a vent extending from the second major surface to the first major surface, the vent providing a pathway for air to escape from between the second major surface and a surface to which the second major surface is to be attached.

Abstract: A leadframe for supporting a semiconductor chip, the leadframe including a die pad having a first major surface and an opposing second major surface defining a thickness and having at least one perimeter edge, and an opening spaced from the at least one perimeter edge and extending through the thickness of the die pad between the first and second major surfaces. A vent extends from the at least one perimeter edge to the opening so that the opening is in communication with the at least one perimeter edge.

Abstract: A smart card for contact data transmission includes a card body and a smart card module which is fitted in the card body. The smart card module includes a semiconductor chip with an active upper surface, a plastic housing compound that surrounds the semiconductor chip and includes at least one surface that is coplanar with the active upper surface of the semiconductor chip, a first dielectric layer that is arranged on the plastic housing compound surface and on the active upper surface of the semiconductor chip, one or more interposer metallization levels, which are isolated via further dielectric layers and are connected to the active upper surface of the semiconductor chip, and external contact surfaces. The external contact surfaces are formed on the outermost interposer level and facilitate contact data transmission. The smart card module uses no bonding wires and has a very small physical volume.

Abstract: A biosensor that has a smart card configuration includes a semiconductor chip including a bioactive structure and contact areas disposed on a first side of the semiconductor chip, and a rewiring substrate including contact pads, external contact areas and rewiring lines that electrically connect the contact pads to the external contact areas. The rewiring substrate covers a portion of the first side of the semiconductor chip without covering the bioactive structure, such that the rewiring substrate overlaps the contact areas of the semiconductor chip and the contact pads and the contact areas are aligned with and electrically connect to each other. In addition, a measuring apparatus is configured to receive the biosensor and conduct measurements of a fluid medium that is delivered into the measuring apparatus.

Abstract: One embodiment of the invention relates to an electronic component having stacked semiconductor chips, and to a panel for production of the component. In one case, the stack has a flat conductor structure with a chip island on which a stacked semiconductor chip is arranged, while a first semiconductor chip is located underneath it. The chip island is surrounded by flat conductors which have contact pillars. These contact pillars have pillar contact pads which, together with the active upper face of the first semiconductor chip and the upper face areas of a plastic encapsulation compound form a coplanar overall upper face.

Abstract: An electronic component and a blank have plastic embedding compounds of a first and a second plastic layer. Semiconductor chips are embedded in the first plastic layer in such a way that their marginal sides are surrounded by a bead. The second plastic layer compensates for the unevenness of a upper boundary of the first plastic layer.