Abstract: A method for reading data from a dynamic memory circuit is provided, wherein at least one memory cell can be addressed via a word line and a bit line, wherein the memory cell is connected to a first reading amplifier via the bit line, and wherein a switching element, which in the off state isolates the first reading amplifier from the bit line, is provided. The method comprises: a) turning on the switching element to connect the first reading amplifier to the bit line, b) activating the word line to activate the memory cell for reading, c) activating the first reading amplifier to initiate assessment of the information on the bit line, d) turning off the switching element to isolate the first reading amplifier from the bit line, and e) transferring the information which has been read to a data bus.

Abstract: A configuration for executing data processing processes has an operating system and various system resources that are accessed by the operating system using an access strategy for the execution of system processes. When there are different applications, different access strategies to the system resources are used. A method is also provided for determining the optimum access strategy to the system resources.

Abstract: The invention relates to a circuit module with high-frequency input/output interfaces, and in particular to a circuit realized on a chip, principally a monolithic integrated circuit having a phase-regulated circuit which is fed by externally applied voltages and an internal operating voltage generated on the basis of a trimmable internal reference voltage. According to the invention, each further internal operating voltage is derived from an individual reference voltage on the basis of an external voltage. An adjusting circuit is provided which adjusts the individual reference voltage using the trimmable internal reference voltage and then freezes it.

Abstract: A method for reading data from a dynamic memory circuit is provided, wherein at least one memory cell can be addressed via a word line and a bit line, wherein the memory cell is connected to a first reading amplifier via the bit line, and wherein a switching element, which in the off state isolates the first reading amplifier from the bit line, is provided. The method comprises: a) turning on the switching element to connect the first reading amplifier to the bit line, b) activating the word line to activate the memory cell for reading, c) activating the first reading amplifier to initiate assessment of the information on the bit line, d) turning off the switching element to isolate the first reading amplifier from the bit line, and e) transferring the information which has been read to a data bus.

Abstract: A memory module is described which, externally, has the functionality of DDR SDRAMs and contains two groups of conventional SDRAMs. A conversion device provides for the conversion of clock signals, commands, and data. The conversion device contains a changeover switch, a delay locked loop and buffer memory for addresses and commands and also for the data, which are driven in a suitable manner by the delay locked loop.

Abstract: In a scalable driver device having a plurality of driver stages whose outputs are connected to a common terminal contact for providing a common output signal, drive parameters of the driver stages, individually or in groups, are so dimensioned that the difference of the edge rise times and/or fall times of the output signal from one active driver stage to the next driver stage to be activated is substantially equal to the difference of the edge rise times and/or fall times from a next activated driver stage to the one activated after that.

Abstract: A circuit configuration for processing data, particularly a semiconductor memory chip, has a control circuit for setting a phase or frequency relationship between two signals. A digital counter detects a phase or frequency difference between the two signals, and the counter reading is used for regulating the phase or frequency relationship. Trials have shown that the counter reading indicates an operating state in the circuit configuration and therefore represents a simple signal for assessing the operating state of the circuit configuration. Preferably, the counter reading is taken as a basis for adjusting the speed or power of time-critical or performance-critical circuit parts in the circuit configuration so that an operating state with an intermediate switching speed is obtained.

Abstract: The data processing system has configurable components, which each have a configuration register for storing configuration data. A serial bus couples the configuration registers to a non-volatile memory so that a serial transmission of data from the non-volatile memory to the configuration registers is made possible, for example when the system is booted up. The system already functions even if complex bus systems, such as extensively parallel high-speed buses, for example, are not yet available in a configuration process of the system. The system can be used in all data processing systems, in particular in mobile applications.

Abstract: A configuration for executing data processing processes has an operating system and various system resources that are accessed by the operating system using an access strategy for the execution of system processes. When there are different applications, different access strategies to the system resources are used. A method is also provided for determining the optimum access strategy to the system resources.

Abstract: A method for driving a plurality of circuit units to be controlled includes applying a control signal to a control signal connection unit and an activation signal to an activation connection unit. A hold signal is the generated on the in response to the activation signal. This hold signal is combined with the control signal to obtain a modified control signal, which is then made available at an output.

Abstract: Programmable voltage pump for producing an output voltage includes a trim input configured to set the output voltage, an output configured to emit the output voltage therefrom, and an activation/deactivation input configured to at least one of activate and deactivate the voltage pump. The activation/deactivation input includes a switch connected to the output, the switch configured to selectively connect a network to ground, the network being connected to the output.

Abstract: An integrated memory has a memory cell array, which is subdivided into a plurality of separate segments. A first and a second local word line in different segments together form a common global word line. The global word line is decoded via a row decoder. The first and second local word lines are connected to a column decoder in such a way that they can be decoded individually and segment by segment in a manner dependent on a column address. The memory thus allows fast and current-saving activation of a word line.

Abstract: A monolithically integrable inductor containing a layer sequence of conductive layers and insulating layers that are stacked mutually alternately above one another is described. The conductive layers are configured in such a way that they form a coil-type structure around a central region, in which giant magnetic resistance materials can be provided.

Abstract: A measurement probe for detecting electrical signals in an integrated circuit on a semiconductor chip has a lever arm and a probe tip which is configured on the lever arm. The lever arm is made of a highly conductive material that is covered by an extremely thin insulator layer. The probe tip has a window in the insulator layer at the apex point, and the lever arm makes contact through the insulator layer. This measurement probe can be operated in a force mode and in a tunneling mode, in order to move to a measurement point on the integrated circuit with high positioning accuracy, and to detect the electrical signals at this measurement point.

Abstract: Programmable voltage pump for producing an output voltage includes a trim input configured to set the output voltage, an output configured to emit the output voltage therefrom, and an activation/deactivation input configured to at least one of activate and deactivate the voltage pump. The activation/deactivation input includes a switch connected to the output, the switch configured to selectively connect a network to ground, the network being connected to the output.

Abstract: A measuring device has a needle-board circuit board carrying a large number of contact-making needles for contacting connecting areas on an IC circuit. The measuring device has lines for feeding test signals at a high clock frequency to the contact-making needles, and for carrying measured signals away from the contact-making needles. The needles have a shank part with a length L2 and a tip part 14 adjacent thereto with a length L1. For optimally transmitting signals in terms of impedance, the lines are formed as dual-transmission conductor tracks, the shank parts of the contact-making needles each contact a section of the conductor tracks, and the overall length of the contact-making needles satisfies: L1+L2<&lgr;/2, where &lgr; is the maximum wavelength of the signal that is transmitted via a respective line.

Abstract: The data processing system has configurable components, which each have a configuration register for storing configuration data. A serial bus couples the configuration registers to a non-volatile memory so that a serial transmission of data from the non-volatile memory to the configuration registers is made possible, for example when the system is booted up. The system already functions even if complex bus systems, such as extensively parallel high-speed buses, for example, are not yet available in a configuration process of the system. The system can be used in all data processing systems, in particular in mobile applications.

Abstract: A circuit configuration for processing data, particularly a semiconductor memory chip, has a control circuit for setting a phase or frequency relationship between two signals. A digital counter detects a phase or frequency difference between the two signals, and the counter reading is used for regulating the phase or frequency relationship. Trials have shown that the counter reading indicates an operating state in the circuit configuration and therefore represents a simple signal for assessing the operating state of the circuit configuration. Preferably, the counter reading is taken as a basis for adjusting the speed or power of time-critical or performance-critical circuit parts in the circuit configuration so that an operating state with an intermediate switching speed is obtained.

Abstract: In a scalable driver device having a plurality of driver stages whose outputs are connected to a common terminal contact for providing a common output signal, drive parameters of the driver stages, individually or in groups, are so dimensioned that the difference of the edge rise times and/or fall times of the output signal from one active driver stage to the next driver stage to be activated is substantially equal to the difference of the edge rise times and/or fall times from a next activated driver stage to the one activated after that.

Abstract: A method for accessing memory cells of a cell field of a DRAM module organized in rows and columns, in which an addressed row is addressed over a word line, and a desired column is addressed over a bit line pair, is described. For a write access, a stored charge is transferred to all bit line pairs, a column address is detected by a column decoder, the appertaining word line is activated, and a read amplifier amplifies the potential on the addressed bit lines. The write access is initiated simultaneously with an activation of the word line.