Patents by Inventor Bernd Schafferer

Bernd Schafferer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210194520
    Abstract: Methods, devices and algorithms for the linearization of nonlinear time variant systems and the synchronization of a plurality of such systems. One embodiment includes a transmit path, including the power amplifier, as used in wireless transmit systems. Advances made in CMOS technology, digital to analog converter (DAC) technology make it possible to implement a substantial part of such a system in the digital domain. Additional embodiments include the integration of a substantial part of such a transmit system in a single integrated circuit (IC). A digital implementation allows for linearization of a broad range of nonlinear and time variant effects. Another aspects is the reuse of methods, devices, components and algorithms used for the linearization of a transmit system to synchronize and time align multiple transmit systems.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 24, 2021
    Applicant: S9ESTRE, LLC
    Inventor: Bernd SCHAFFERER
  • Patent number: 10230387
    Abstract: Converter circuits and methods herein describe mechanisms for converting a digital input signal to an analog output signal using a series of transmission lines. The circuits and methods described herein convert to analog signal using very little power, due to inter-coupling of wave propagation media.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: March 12, 2019
    Assignee: S9ESTRE, LLC
    Inventor: Bernd Schafferer
  • Publication number: 20180241311
    Abstract: Methods and devices for power conversion. High frequency electromagnetic waves traveling in coupled transmission lines and their reflective properties are used to perform the power conversion. The use of high frequency operation allows for physically small transmission lines. The high operating frequencies also allow for small filter capacitors at the outputs of the power converter and hence allowing for fast response times in load changes or fast signal changes in case of a gate driver. The transmission lines can be implemented on the printed circuit board, laminate or even on chip. In case of a step up converter the switching elements are not subjected to the higher output voltage levels of the power converter and can therefore be implemented in a lower voltage process technology. Further, embodiments with and without galvanic isolation are described and physical embodiments to reduce undesired electromagnetic emissions are disclosed.
    Type: Application
    Filed: July 1, 2016
    Publication date: August 23, 2018
    Applicant: S9estre, LLC
    Inventor: Bernd SCHAFFERER
  • Publication number: 20180241412
    Abstract: Converter circuits and methods herein describe mechanisms for converting a digital input signal to an analog output signal using a series of transmission lines. The circuits and methods described herein convert to analog signal using very little power, due to inter-coupling of wave propagation media.
    Type: Application
    Filed: August 12, 2016
    Publication date: August 23, 2018
    Applicant: S9ESTRE, LLC
    Inventor: Bernd SCHAFFERER
  • Patent number: 10056924
    Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: August 21, 2018
    Assignee: ANALOG DEVICES, INC.
    Inventors: Bernd Schafferer, Bing Zhao
  • Patent number: 9859906
    Abstract: Methods and devices for an energy efficient digital to analog conversion are disclosed. With the achievable sampling rates and output voltage levels, high power RF signals can be synthesized. A plurality of pulses are generated and coupled onto transmission lines. On the other end of the transmission line the pulses are either reflected or transmitted to a load line depending on the status of a termination element. In one embodiment the reflected pulses are collected and sent to a load. The energy in the transmitted pulses can be recovered and reused. In another embodiment the transmitted pulses are collected and transmitted to a load and the energy in the reflected pulses is recovered and reused.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: January 2, 2018
    Assignee: S9ESTRE, LLC
    Inventor: Bernd Schafferer
  • Publication number: 20170230055
    Abstract: Methods and devices for an energy efficient digital to analog conversion are disclosed. With the achievable sampling rates and output voltage levels, high power RF signals can be synthesized. A plurality of pulses are generated and coupled onto transmission lines. On the other end of the transmission line the pulses are either reflected or transmitted to a load line depending on the status of a termination element. In one embodiment the reflected pulses are collected and sent to a load. The energy in the transmitted pulses can be recovered and reused. In another embodiment the transmitted pulses are collected and transmitted to a load and the energy in the reflected pulses is recovered and reused.
    Type: Application
    Filed: August 11, 2015
    Publication date: August 10, 2017
    Applicant: S9ESTRE, LLC
    Inventor: Bernd SCHAFFERER
  • Patent number: 9444401
    Abstract: Methods and devices for the generation of high frequency clock signals. In a transmission line a signal is reflected back and forward. The electric length of the transmission line determines the frequency of the oscillation. A start signal at the switching device initiates a signals traveling down the transmission line. At the other end of the transmission line the signals is reflected back. At the tapping point along the transmission line, part of the energy of the signal in the transmission line is coupled out to form the feedback signal. The feedback signal activates the switching device. The switching device injects energy into the transmission line and sustains the oscillation on the transmission line. The position of the tapping point on transmission line determines the shape of the feedback signals and can hence be used as a design parameter optimize the performance of the system.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: September 13, 2016
    Assignee: S9ESTRE, LLC
    Inventor: Bernd Schafferer
  • Patent number: 9344104
    Abstract: Methods and devices for the calibration of digital to analog converters (DAC) and analog to digital converters (ADC) are disclosed. In a first step the DAC is calibrated and in a second step the calibrated DAC is used to calibrate the ADC. Averaging techniques and/or equation based techniques are used to further improve the calibration of both components in an iterative process. Embodiments of the invention allow for a very compact physical implementations of the converter. The invention reduces of analog circuitry in favor of digital circuits. Embodiments of the invention are suitable for the implementation in fine line CMOS processes and can operate in a low supply voltage environment.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: May 17, 2016
    Assignee: S9ESTRE, LLC
    Inventor: Bernd Schafferer
  • Publication number: 20160134302
    Abstract: Methods and devices for the calibration of digital to analog converters (DAC) and analog to digital converters (ADC) are disclosed. In a first step the DAC is calibrated and in a second step the calibrated DAC is used to calibrate the ADC. Averaging techniques and/or equation based techniques are used to further improve the calibration of both components in an iterative process. Embodiments of the invention allow for a very compact physical implementations of the converter. The invention reduces of analog circuitry in favor of digital circuits. Embodiments of the invention are suitable for the implementation in fine line CMOS processes and can operate in a low supply voltage environment.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 12, 2016
    Inventor: Bernd Schafferer
  • Patent number: 9300462
    Abstract: Methods, devices and algorithms for the linearization of nonlinear time variant systems and the synchronization of a plurality of such systems. An example of such a system would be a transmit path, including the power amplifier, as used in wireless transmit systems. Advances made in CMOS technology, digital to analog converter (DAC) technology make it possible to implement a substantial part of such a system in the digital domain. Another aspect is the integration of a substantial part of such a transmit system in a single integrated circuit (IC). A digital implementation that allows for linearization of a broad range of nonlinear and time variant effects. Since this digital implementations operate a high clock frequency a energy efficient implementation is essential to keep the power consumption under control. Another aspects is the reuse of methods, devices and algorithms used for the linearization a transmit system to synchronize multiple transmit systems.
    Type: Grant
    Filed: May 17, 2014
    Date of Patent: March 29, 2016
    Inventor: Bernd Schafferer
  • Patent number: 9281788
    Abstract: Power efficiency is an important design requirement of power amplifiers. To improve power efficiency, a solution proposed in this present disclosure includes an all-digital zero-voltage switching apparatus for directly driving a switching power amplifier through a desired current pulse shape. The apparatus includes a digital engine and a digital-to-analog converter (DAC). The digital engine processes baseband data and generates a digital output. The digital output of the digital engine drives the DAC to generate a digitally controlled current output having that desired current pulse shape. The digitally controlled current output is used to directly drive the switch power amplifier to improve power efficiency. The digitally controlled current output comprising digitally generated current pulses is controlled accurately by the digital engine and the DAC, and thus allows the switching power amplifier to operate optimally with higher power efficiency than conventional power amplifiers.
    Type: Grant
    Filed: March 8, 2014
    Date of Patent: March 8, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventors: Bernd Schafferer, Bing Zhao
  • Patent number: 9276617
    Abstract: Digital pre-distortion (DPD) systems are often used to improve the linearity of a power amplifier in transmitters. These DPD systems are typically implemented in baseband (prior to modulation). However, ever increasing signal bandwidth requirements limits the practicality of DPD systems implemented in baseband. A DPD system in the radio frequency (RF) domain (as opposed to in baseband) can solve this problem and further improve a DPD system's ability to correct for distortions. The RF domain DPD system is upstream from a digital-to-analog converter, and performs DPD after a baseband signal is up-sampled into the RF domain (after the modulation process). When compared against a baseband DPD system, the RF domain DPD system can handle significantly wider bandwidth, and has an improved ability to linearize a wide variety of distortions present in the spectrum.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: March 1, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventors: Bernd Schafferer, Bing Zhao
  • Patent number: 9154148
    Abstract: In an example, there is disclosed herein a digital-to-analog converter (DAC) including a correction circuit for a clock, including a differential clock. Error correction may take place within the DAC core, by means of replica cells that are substantially similar to conversion cells. Rather than contributing their output to the converted signal, the replica cells may be configured to provide a feedback signal to a clock receiver with information for correcting the clock signal. The feedback signal may be operable to correct errors, for example, in duty cycle and crosspoint, as measured at the DAC core.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: October 6, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventors: Bernd Schafferer, Ping Wing Lai, Qiurong He
  • Publication number: 20150171878
    Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).
    Type: Application
    Filed: February 23, 2015
    Publication date: June 18, 2015
    Applicant: ANALOG DEVICES, INC.
    Inventors: Bernd Schafferer, Bing ZHAO
  • Patent number: 8970418
    Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 3, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Bernd Schafferer, Bing Zhao
  • Publication number: 20150048961
    Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).
    Type: Application
    Filed: March 21, 2014
    Publication date: February 19, 2015
    Applicant: ANALOG DEVICES, INC.
    Inventors: Bernd SCHAFFERER, Bing ZHAO
  • Publication number: 20140376676
    Abstract: Methods, devices and algorithms for the linearization of nonlinear time variant systems and the synchronization of a plurality of such systems. An example of such a system would be a transmit path, including the power amplifier, as used in wireless transmit systems. Advances made in CMOS technology, digital to analog converter (DAC) technology make it possible to implement a substantial part of such a system in the digital domain. Another aspect is the integration of a substantial part of such a transmit system in a single integrated circuit (IC). A digital implementation that allows for linearization of a broad range of nonlinear and time variant effects. Since this digital implementations operate a high clock frequency a energy efficient implementation is essential to keep the power consumption under control. Another aspects is the reuse of methods, devices and algorithms used for the linearization a transmit system to synchronize multiple transmit systems.
    Type: Application
    Filed: May 17, 2014
    Publication date: December 25, 2014
    Inventor: Bernd Schafferer
  • Publication number: 20140313065
    Abstract: In an example, there is disclosed herein a digital-to-analog converter (DAC) including a correction circuit for a clock, including a differential clock. Error correction may take place within the DAC core, by means of replica cells that are substantially similar to conversion cells. Rather than contributing their output to the converted signal, the replica cells may be configured to provide a feedback signal to a clock receiver with information for correcting the clock signal. The feedback signal may be operable to correct errors, for example, in duty cycle and crosspoint, as measured at the DAC core.
    Type: Application
    Filed: March 13, 2014
    Publication date: October 23, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventors: BERND SCHAFFERER, PING WING LAI, QIURONG HE
  • Patent number: RE47601
    Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: September 10, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Bernd Schafferer, Bing Zhao