Abstract: Power efficiency is an important design requirement of power amplifiers. To improve power efficiency, a solution proposed in this present disclosure includes an all-digital zero-voltage switching apparatus for directly driving a switching power amplifier through a desired current pulse shape. The apparatus includes a digital engine and a digital-to-analog converter (DAC). The digital engine processes baseband data and generates a digital output. The digital output of the digital engine drives the DAC to generate a digitally controlled current output having that desired current pulse shape. The digitally controlled current output is used to directly drive the switch power amplifier to improve power efficiency. The digitally controlled current output comprising digitally generated current pulses is controlled accurately by the digital engine and the DAC, and thus allows the switching power amplifier to operate optimally with higher power efficiency than conventional power amplifiers.

Abstract: Digital pre-distortion (DPD) systems are often used to improve the linearity of a power amplifier in transmitters. These DPD systems are typically implemented in baseband (prior to modulation). However, ever increasing signal bandwidth requirements limits the practicality of DPD systems implemented in baseband. A DPD system in the radio frequency (RF) domain (as opposed to in baseband) can solve this problem and further improve a DPD system's ability to correct for distortions. The RF domain DPD system is upstream from a digital-to-analog converter, and performs DPD after a baseband signal is up-sampled into the RF domain (after the modulation process). When compared against a baseband DPD system, the RF domain DPD system can handle significantly wider bandwidth, and has an improved ability to linearize a wide variety of distortions present in the spectrum.

Abstract: In one embodiment, digital-to-analog converter (DAC) circuit includes dual DAC units employing pseudo-return-to-zero DAC operations to reduce inter-symbol interference. Moreover, each DAC unit is implemented using complementary MOS transistors to improve conversion performance. In another embodiment, a DAC calibration scheme performs background calibration of an array of DAC circuits in continuous time using a reference DAC circuit and a spare DAC circuit. Calibration (also referred to as “trimming”) of the DAC circuit using the calibration scheme of the present invention ensures that the DAC operates with high linearity over process variations. In one embodiment, the DAC circuit and the DAC calibration scheme are applied as the feedback DAC in a continuous-time sigma-delta (CT-??) analog-to-digital converter to realize high performance and high precision analog-to-digital conversions.

Abstract: A method for generating a data signal for synchronizing one or more electrically coupled digital receivers is disclosed. A data signal having a data rate is modulated with a pseudo-noise (PN) code having a data rate greater than the data rate of the data signal. The modulated data signal is demodulated by a receiver using the PN code. A correlation value is generated and is compared to a predetermined value to indicate phase synchronization. If the receiver is in phase synchronization with the transmitter, the received demodulated data signal is passed.

Abstract: An electronic chip has a data input for receiving an input digital data signal with a data frequency, a plurality of switches, and a logic circuit operatively coupled with both the plurality of switches and the data input. The logic circuit controls the switches to be in one of a DAC mode or a mixer mode. The DAC mode causes the switches to convert the input digital data signal into a DAC analog signal having about the data frequency. The mixer mode, however, causes the switches to convert the input digital data signal into a mixed analog signal having a mixer frequency that is higher than the data frequency.

Abstract: An electronic chip has a data input for receiving an input digital data signal with a data frequency, a plurality of switches, and a logic circuit operatively coupled with both the plurality of switches and the data input. The logic circuit controls the switches to be in one of a DAC mode or a mixer mode. The DAC mode causes the switches to convert the input digital data signal into a DAC analog signal having about the data frequency. The mixer mode, however, causes the switches to convert the input digital data signal into a mixed analog signal having a mixer frequency that is higher than the data frequency.

Abstract: A method for generating a data signal for synchronizing one or more electrically coupled digital receivers is disclosed. A data signal having a data rate is modulated with a pseudo-noise (PN) code having a data rate greater than the data rate of the data signal. The modulated data signal is demodulated by a receiver using the PN code. A correlation value is generated and is compared to a predetermined value to indicate phase synchronization. If the receiver is in phase synchronization with the transmitter, the received demodulated data signal is passed.

Abstract: Methods and devices for code independent switching in signal processing circuit such as a digital-to-analog converter (DAC) are described, which provide code independent switching activity. A steering cell receives a digital data input signal that is defined at data intervals, and produces multiple representative analog output signals. For each data interval, each analog output signal depends only on the present state of the digital data input signal, independently of any previous state of the digital data input signal. In addition, the signal processing circuit apart from the analog output signals is substantially free of data dependent disturbances.

Abstract: Described is a differential clock receiver comprising a converter, a differential input stage, and a differential output stage. The converter converts a control signal indicative of a timing relationship into a DC offset signal. The differential input stage receives a differential clock signal and the DC offset signal. The differential input stage generates an intermediary differential signal from the differential clock. The intermediary differential signal has a DC offset resulting from the DC offset signal. The differential output stage receives the intermediary differential signal and generates at least two output signals from the intermediary differential signal. The output signals have a timing relationship determined by the DC offset of the intermediary differential signal.

Abstract: A system and method are provided for controlling the on/off timing relationship between two transistors in a differential that are connected at a tail node to a common current generator. The on/off timing relationship is controlled by on/off signals that control the state of the transistors such that one transistor turns one while the other is turning off. An overlap signal is derived from the tail node excursion and is indicative of whether the on/off signals are overlapping too much or too little. A control signal is generated based on the overlap signal. The timing of driver signals used to derive the on/off signals is adjusted based on the control signal. When more overlap is needed, the timing of the driver signals is adjusted such that there is more overlap of the derived on/off signals. When less overlap is needed, the timing of the driver signals is adjusted such that there is less overlap of the derived on/off signals.

Abstract: A method and apparatus for synchronizing actions of two circuits or two parts of one circuit where each circuit utilizes a different clock signal. More than one clock signal are derived from a master clock signal and run at the same frequency but have an unknown or variable phase difference. The invention solves the problem of coupling two clocked circuits where synchronization is required to properly read or sample a signal from a data line connecting the two circuits. An error window is defined during which sampling is suppressed, for example to avoid sampling during data transitions. The method of apparatus involves time shifting a pseudo-signal to generate two time-shifted signals and then defining the error window as the time during which the two time-shifted signals differ from one another.

Abstract: Methods and devices for code independent switching in signal processing circuit such as a digital-to-analog converter (DAC) are described, which provide code independent switching activity. A steering cell receives a digital data input signal that is defined at data intervals, and produces multiple representative analog output signals. For each data interval, each analog output signal depends only on the present state of the digital data input signal, independently of any previous state of the digital data input signal. In addition, the signal processing circuit apart from the analog output signals is substantially free of data dependent disturbances.

Abstract: A method and apparatus for synchronizing actions of two circuits or two parts of one circuit where each circuit utilizes a different clock signal are presented. In some embodiments, more than one clock signal are derived from a master clock signal and run at the same frequency but have an unknown or variable phase difference. Some aspects of the invention solve the problem of coupling two clocked circuits where synchronization is required to properly read or sample a signal from a data line connecting the two circuits. In some embodiments, an error window is defined during which sampling is suppressed, for example to avoid sampling during data transitions. One embodiment involves time shifting a pseudo-signal to generate two time-shifted signals and then defining the error window as the time during which the two time-shifted signals differ from one another.

Abstract: A system and method are provided for controlling the on/off timing relationship between two transistors in a differential that are connected at a tail node to a common current generator. The on/off timing relationship is controlled by on/off signals that control the state of the transistors such that one transistor turns one while the other is turning off. An overlap signal is derived from the tail node excursion and is indicative of whether the on/off signals are overlapping too much or too little. A control signal is generated based on the overlap signal. The timing of driver signals used to derive the on/off signals is adjusted based on the control signal. When more overlap is needed, the timing of the driver signals is adjusted such that there is more overlap of the derived on/off signals. When less overlap is needed, the timing of the driver signals is adjusted such that there is less overlap of the derived on/off signals.