Abstract: An intermetal dielectric and metal layers embedded in the intermetal dielectric are arranged on a substrate of semiconductor material. A via hole is formed in the substrate, and a metallization contacting a contact area of one of the metal layers is applied in the via hole. The metallization, the metal layer comprising the contact area and the intermetal dielectric are partially removed at the bottom of the via hole in order to form a hole penetrating the intermetal dielectric and extending the via hole. A continuous passivation is arranged on sidewalls within the via hole and the hole, and the metallization contacts the contact area around the hole. Thus the presence of a thin membrane of layers, which is usually formed at the bottom of a hollow through-substrate via, is avoided.

Abstract: An intermetal dielectric and metal layers embedded in the intermetal dielectric are arranged on a substrate of semiconductor material. A via hole is formed in the substrate, and a metallization contacting a contact area of one of the metal layers is applied in the via hole. The metallization, the metal layer comprising the contact area and the intermetal dielectric are partially removed at the bottom of the via hole in order to form a hole penetrating the intermetal dielectric and extending the via hole. A continuous passivation is arranged on sidewalls within the via hole and the hole, and the metallization contacts the contact area around the hole. Thus the presence of a thin membrane of layers, which is usually formed at the bottom of a hollow through-substrate via, is avoided.

Abstract: A dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1), and a passivation layer (6) is arranged on the dielectric layer. A metal layer (3) is embedded in the dielectric layer above an opening (12) in the substrate, and a metallization (14) is arranged in the opening. The metallization contacts the metal layer and forms a through-substrate via to a rear surface (11) of the substrate. A layer or layer sequence (7, 8, 9) comprising at least one further layer is arranged on the passivation layer above the opening. In this way the bottom of the through-substrate via is stabilized. A plug (17) may additionally be arranged in the opening without filling the opening.

Abstract: An opening (17) is etched from a main surface (10) of a substrate (1) of semiconductor material by deep reactive ion etching comprising a plurality of cycles, each of the cycles including a deposition of a passivation in the opening and an application of an etchant. An additional etching is performed between two consecutive cycles by an application of a further etchant that is different from the etchant. The passivation layer (9) is thus etched above a sidewall (7) of the opening to remove undesired protrusions.

Abstract: An opening (17) is etched from a main surface (10) of a substrate (1) of semiconductor material by deep reactive ion etching comprising a plurality of cycles, each of the cycles including a deposition of a passivation in the opening and an application of an etchant. An additional etching is performed between two consecutive cycles by an application of a further etchant that is different from the etchant. The passivation layer (9) is thus etched above a sidewall (7) of the opening to remove undesired protrusions.

Abstract: A dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1), and a passivation layer (6) is arranged on the dielectric layer. A metal layer (3) is embedded in the dielectric layer above an opening (12) in the substrate, and a metallization (14) is arranged in the opening. The metallization contacts the metal layer and forms a through-substrate via to a rear surface (11) of the substrate. A layer or layer sequence (7, 8, 9) comprising at least one further layer is arranged on the passivation layer above the opening. In this way the bottom of the through-substrate via is stabilized. A plug (17) may additionally be arranged in the opening without filling the opening.

Abstract: A micromechanical component that can be produced in an integrated thin-film method is disclosed, which component can be produced and patterned on the surface of a substrate as multilayer construction. At least two metal layers that are separated from the substrate and with respect to one another by interlayers are provided for the multilayer construction. Electrically conductive connecting structures provide for an electrical contact of the metal layers among one another and with a circuit arrangement arranged in the substrate. The freely vibrating membrane that can be used for an inertia sensor, a microphone or an electrostatic switch can be provided with matching and passivation layers on all surfaces in order to improve its mechanical properties, said layers being concomitantly deposited and patterned during the layer producing process or during the construction of the multilayer construction. Titanium nitride layers are advantageously used for this.

Abstract: A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer.

Abstract: A transistor includes an emitter, a collector, and a base layer having a base contact. The base layer includes an intrinsic region between the emitter and the collector, an extrinsic region between the intrinsic region and the base contact, and a first doping layer that is doped with a trivalent substance, that extends into the extrinsic region, and that is counter-doped with a pentavalent substance in a region adjacent to the emitter.

Abstract: A micromechanical component that can be produced in an integrated thin-film method is disclosed, which component can be produced and patterned on the surface of a substrate as multilayer construction. At least two metal layers that are separated from the substrate and with respect to one another by interlayers are provided for the multilayer construction. Electrically conductive connecting structures provide for an electrical contact of the metal layers among one another and with a circuit arrangement arranged in the substrate. The freely vibrating membrane that can be used for an inertia sensor, a microphone or an electrostatic switch can be provided with matching and passivation layers on all surfaces in order to improve its mechanical properties, said layers being concomitantly deposited and patterned during the layer producing process or during the construction of the multilayer construction. Titanium nitride layers are advantageously used for this.

Abstract: The invention relates to a transistor having an emitter (1), a collector (2), and a base layer (3), wherein the emitter (1) extends into the base layer (3), wherein the base layer (3) has an intrinsic region (4) arranged between the emitter (1) and the collector (2), and an extrinsic region (6) that runs between the intrinsic region (4) and a base contact (5), wherein the base layer (3) contains a first doping layer (7) doped with a trivalent doping substance, which extends into the extrinsic region (6) and which is counter-doped by means of a pentavalent counter-doping substance (8) in the region of the emitter (1). The electrical resistance of the base layer (3) can be reduced, in advantageous manner, by means of the first doping layer (7).