Integration of Multiple Gate Oxides with Shallow Trench Isolation Methods to Minimize Divot Formation
A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer.
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The present disclosure generally relates to microelectronics. In one embodiment, the present invention relates to a method of reducing divot formation in producing shallow trench isolation (STI) regions.
BACKGROUNDAs semiconductor device dimensions are decreased, and device density increases, it becomes more difficult to efficiently and reliably fabricate isolation structures for separating active areas of the device. One common method of forming isolation structures for semiconductor devices is referred to as localized oxidation of silicon (LOCOS). However, the limits of the standard LOCOS process have motivated the development of new isolation processes.
Shallow trench isolation (STI) has become the most common and important isolation technology for sub-quarter micron complementary metal oxide semiconductor (CMOS) devices. Conventional STI processes include corner rounding and divot formation (i.e., oxide recess) along STI edges. In some scenarios, the divot at the edge of the STI is formed due to wet dip of a pad oxide by an HF solution.
SUMMARYA method of forming an isolation region is provided that in one embodiment includes forming a first pad dielectric layer on an upper surface of a semiconductor substrate; forming a trench through the first pad dielectric layer into the semiconductor substrate; laterally etching the first pad dielectric layer to expose the upper surface of the semiconductor substrate adjacent the trench; filling the trench with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the substrate adjacent the trench and abutts the pad dielectric layer; removing the first pad dielectric layer to provide an exposed portion of the upper surface of the substrate that is adjacent the trench dielectric material that extends atop the upper surface of the semiconductor substrate; and forming a conformal dielectric layer overlying the exposed portion of the semiconductor substrate and the trench dielectric material.
In another aspect, the method includes providing a forming a pad stack on an upper surface of a semiconductor substrate, the pad stack including a second pad dielectric layer atop the semiconductor substrate and a first pad dielectric layer atop the second pad dielectric layer; forming at least a first trench and a second trench through the pad stack into the semiconductor substrate; forming an etch mask dielectric layer on a base and sidewall of the first trench and a portion of the pad stack adjacent to the first trench; etching the pad stack using the etch mask dielectric layer as an etch mask to provide an exposed portion of the upper surface of the semiconductor substrate that is adjacent to the second trench in which the etch mask dielectic layer is not present; and filling the first trench and the second trench with a trench dielectric material, wherein a portion of the trench dielectric material is present on the exposed portion of the upper surface of the semiconductor substrate.
In another aspect of the present invention, divot reduction in isolation region formation may be realized by a process in which a thermal oxide layer having a thickness on the order of 40 nm or greater is formed prior to etch processes that define the active device region of the substrate. In one embodiment, this aspect includes thermally growing an oxide pad dielectric layer on a semiconductor substrate, wherein the oxide pad dielectric layer has a thickness greater than 40 nm; patterning the oxide pad dielectric layer to provide a via to an exposed surface of the semiconductor substrate that is overlying at least a portion of the active device region of the semiconductor substrate; forming a gate dielectric on the exposed surface of the semiconductor substrate; and forming a trench isolation region extending through the oxide pad dielectric into a portion of the semiconductor substrate that is abutting the active device region of the semiconductor substrate.
The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, wherein like reference numerals denote like elements and parts, in which:
The present invention in at least one embodiment provides methods of forming isolation regions, such as shallow trench isolation (STI) regions, without forming divots at the interface of the dielectric material and the semiconductor material.
Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the invention that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments of the invention is intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be appreciated by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the invention.
When describing the methods and structures of the present invention, the following terms have the following meanings, unless otherwise indicated.
As used herein, the term “dielectric” denotes a non-metallic material having insulating properties.
As used herein, the terms “insulating” and “electrically insulates” denote a room temperature conductivity of less than 10−10(Ωm)−1.
As used herein, the term “divot” denotes a recess that is present at the interface of an isolation region and a semiconductor layer that extends from an exterior surface of the interface between the semiconductor layer and the isolation region to an interior depth.
References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the invention, as it is oriented in the drawing figures.
Further, it will be understood that when an element as a layer, region or substrate is referred to as being “atop” or “over” or “overlying” or “below” or “underlying” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” or in “direct physical contact” with another element, there are no intervening elements present.
In one embodiment, the semiconductor substrate 5 employed in the present invention may be any semiconducting material including, but not limited to Si, Ge, SiGe, SiC, SiGeC, Ga, GaAs, InAs, InP and all other III/V or II/VI compound semiconductors. The semiconductor substrate 5 may also include an organic semiconductor or a layered semiconductor, such as Si/SiGe, a silicon-on-insulator (SOI) or a SiGe-on-insulator (SGOI). In some embodiments of the present invention, the semiconductor substrate 5 is composed of a Si-containing semiconductor material, i.e., a semiconductor material that includes silicon. The semiconductor substrate 5 may be doped, undoped or contain doped and undoped regions therein. The semiconductor substrate 5 may also include a first doped (n- or p-) region, and a second doped (n- or p-) region. For clarity, the doped regions are not specifically shown in the drawings of the present application. The first doped region and the second doped region may be the same, or they may have different conductivities and/or doping concentrations. These doped regions are known as “wells”.
In one embodiment, the pad dielectric layer 10 is composed of a nitride material. One example of a nitride material suitable for use as the pad dielectric layer 10 is silicon nitride. In another embodiment, the pad dielectric layer 10 may be an oxide, such as tetraethyl orthosilicate (TEOS), CVD-oxide, or borophosphosilicate glass (BPSG), or a combination of oxide and nitride layers. It is noted that other compositions for the pad dielectric layer 10 have also been contemplated, so long as, the composition selected provides a degree of etch selectivity relative to the underlying materials.
In one embodiment, the pad dieletric layer 10 can be formed using deposition processes, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition and chemical deposition. Alternatively, the pad dielectric layer 10 may be grown, e.g., grown using thermal oxidation and/or nitridation. In one embodiment, the pad dielectric layer 10 can have a thickness ranging from 10 nm to 500 nm. In another embodiment, the pad dielectric layer 10 may have a thickness ranging from 20 nm to 100 nm.
Further, in some embodiments, a second pad dielectric layer (not shown) may be present between the pad dielectric layer 10 and the semiconductor substrate 5. In the embodiments in which the pad dielectric layer 10, i.e., first pad dielectric layer of the pad stack 9, is composed of a nitride, the second pad dielectric layer is composed of an oxide, such as silicon oxide. In one embodiment, the second pad dielectric layer can have a thickness ranging from 5 nm to 15 nm. In another embodiment, the second dielectric layer can have a thickness of 10 nm or less. It is noted that the pad stack 9 has been contemplated to include any number of dielectric layers and it is not intended that the present invention be limited to pad stack 9 described above.
The trench 15 may be formed by an etch process that etches through the pad stack 9 into the semiconductor substrate 5. In one embodiment, following the formation of the pad stack 9, a mask (not shown) is formed on a predetermined portion of the pad stack 9, so as to protect a portion of the pad stack, while leaving another portion of the pad stack 9 that is overlying the subsequently formed trench 15 unprotected. The mask may be formed by applying a photoresist layer (not shown) to the entire surface of pad stack 9, wherein after application of the photoresist layer, the mask is patterned by lithography, which includes the steps of exposing the photoresist to a pattern of radiation and developing the pattern utilizing a resist developer. After providing the mask, the structure is subjected to one or more etching steps so as to define the trench 15 within the semiconductor substrate 5. The etching may include a dry etching process, such as reactive-ion etching, ion beam etching, plasma etching or laser etching. In one embodiment, using a photoresist and masking process as described above allows for multiple sizes of trench to be formed on the same wafer.
In one embodiment, the width W1 of the trench 15 ranges from 50 nm to 10 μm. In another embodiment, the width W1 of the trench 15 ranges from 70 nm to 500 μm. In an even further embodiment, the width W1 of the trench 15 ranges from 70 nm to 200 nm.
In one embodiment, the depth D1 of the trench 15 ranges from 50 nm to 10 μm, as measured from the upper surface of the semiconductor substrate 5. In another embodiment, the depth D1 of the trench 15 ranges from 70 nm to 500 nm. In an even further embodiment, the depth D1 of the trench 15 ranges from 70 nm to 200 nm.
Following etching, the mask may be removed with a chemical clean or by oxygen ashing. The resultant structure after the etching process has been performed is shown, for example, in
In one embodiment, the step of laterally etching the pad dielectric layer 10 to expose the upper surface 20 of the semiconductor substrate 5 that is adjacent to the trench 15 includes a wet etchant appropriate for removing the dielectric material of the pad dielectric layer 10. In one example, in which the pad dielectric layer 10 is composed of a nitride material, such as silicon nitride, the laterally etching of the pad dielectric layer 10 may be conducted using a nitride etch process. The nitride etch is achieved with a combination of hydrofluoric acid (HF) and phosphoric acid. In one example, an etch chemistry for selectively etching silicon nitride includes isotropic wet etches of phosphoric acid (H3PO4) and hydrofluoric acid, which are selective with respect to silicon oxide, organic polymers, polysilicon, silicon, and metals. In one embodiment, these etches are effected by immersing the wafer in an aqueous solution of HF or H3PO4 at temperatures of 80° C. or more. In some embodiments of the invention, in which the etch chemistry includes hydrofluoric acid, the etch temperature is on the order of 100° C. or more. In embodiments of the invention, in which the etch chemistry includes phosphoric acid etches, the etch temperature may be on the order of 100° C. or more, and in some examples greater than 180° C.
In some examples, when performing a phosphoric acid etch, it is desirable to maintain the concentration of etchant in solution with reflux. Refluxed, boiling phosphoric acid at 180° C. has been found in some instances to provide an etch rate of up to 100 Å per minute for silicon nitride films. Deposited silicon dioxide has an etch rate of about 10 Å per minute, and in some instances deposited silicon dioxide may have an etch rate ranging from 0 Å per minute to 25 Å per minute depending upon temperature and preparation. Elemental silicon has an etch rate of about 3 Å per minute. For temperatures ranging from 140-200° C., etch rates increase with temperature.
Water content of the phosphoric acid plays an important role in etching of silicon nitride and silicon dioxide. At a constant temperature, addition of water increases the etch rate of silicon nitride and decreases the etch rate of silicon dioxide.
Because the nitride etch removes nitride from all directions, the pad dielectric layer 10 is thinned by the nitride etch. In one embodiment, the pad dielectric layer 10 is thinned by a dimension T2 ranging from 10 nm to 70 nm, as measured from an upper surface of the pad dielectric layer 10. In another embodiment, the pad dielectric layer 10 is thinned by a dimension T2 ranging from 10 nm to 70 nm.
Referring to
The planarization process may be used to provide a planar structure, in which the upper surface of the trench dielectric material 25 within the trench is coplanar with the pad dielectric layer 10. As used herein, “planarization” is a material removal process that employs at least mechanical forces, such as frictional media, to produce a planar surface. One example of a planarization process is chemical mechanical planarization (CMP). “Chemical mechanical planarization” is a material removal process using both chemical reactions and mechanical forces to remove material and planarize a surface.
In one embodiment, following the filling of the trench 15 with the trench dielectric material 25 and planarization, an upper surface of the trench dielectric material 25 is treated with a etch process that includes a hydrofluoric (HF) acid composition. This process step may recess the upper surface of the trench dielectric material 25 below the upper surface of the pad dielectric layer 10. For example, the upper surface of the trench dielectric material 25 may be recessed 2 nm to 5 nm from the upper surface of the pad dielectric layer 10 by the etch process, as depicted in
Referring to
The second dielectric layer 36 that is formed atop the semiconductor substrate 5, may be an oxide material that may range from 2.5 nm to 5.0 nm thick. The second dielectric layer 36 is formed using conventional techniques, such as chemical vapor deposition (CVD), atomic layer CVD (ALCVD), pulsed CVD, plasma of photo assisted CVD, sputtering, and chemical solution deposition, or alternatively, the second dielectric layer 36 is formed by thermal growing process, which may include oxidation, oxynitridation, nitridation, and/or plasma or radical treatment. Suitable examples of oxides that can be employed as conformal dielectric layer 35 include, but are not limited to SiO2, Al2O3, ZrO2, HfO2, Ta2O3, TiO2, perovskite-type oxides and combinations and multi-layers thereof. It is noted that the second dielectric layer 36 may also be composed of a high-k dielectric material, wherein high-k dielectric materials have a dielectric constant of 3.9 or greater, typically on the order of 4.0, and in some instances greater than 7.0.
Following the formation of the second dielectric layer 36, the structure may then be processed to provide a microelectronic structure wherein the isolation region 100 provides for electrical isolation between adjacent devices, such as semiconductor devices, or components. In one embodiment, the laterally etching of the pad dielectric layer 10, i.e., an extended nitride etch, e.g., nitride pull back process, that exposed the portion of upper surface 20 of the semiconductor substrate 5 having a length L1 ranging from 10 nm to 70 nm that is extending from and adjacent to the trench 15, substantially reduces divot formation at the interface of the semiconductor substrate 5 and the trench dielectric material 25 within the trench 15.
Prior to the present discovery, isolation region formation that did not include the above process sequence resulted in a recess, i.e., divot, at the interface of the trench dielectric material that filled the trench of the isolation region and the semiconductor substrate material in which the trench was formed. It has been determined that divot formation disadvantageously reduces device performance. In one example, in which the divots have been eliminated, the threshold voltage can be differentiated by a value up to 50% of the threshold voltage when compared to similar devices in which divots are not present. Further, the reliability of the gate dielectric, e.g., gate oxide, can be reduced by gate thinning by the wet etch steps that result in divot formation. In addition to reducing divot formation in low voltage devices, e.g., semiconductor devices having a gate oxide thickness below 200 Å, the present invention also increases electrical isolation of high voltage devices, in which the gate oxide thickness is greater than 200 Å, by extending the dielectric material, i.e., trench dielectric material 25, atop the portion of the semiconductor substrate 5 that is exposed by the laterally etching of the pad dielectric layer 10.
Referring to
The etch mask dielectric layer 65 may be an oxide material that typically range from 2.5 nm to 5.0 nm thick. The etch mask dielectric layer 65 may be formed using deposition techniques, such as chemical vapor deposition (CVD), atomic layer CVD (ALCVD), pulsed CVD, plasma of photo assisted CVD, sputtering, and chemical solution deposition, or alternatively, the etch mask dielectric layer 65 is formed by thermal growing process, which may include oxidation, oxynitridation, nitridation, and/or plasma or radical treatment. Suitable examples of oxides that can be employed as the etch mask dielectric layer 65 include, but are not limited to: SiO2, Al2O3, ZrO2, HfO2, Ta2O3, TiO2, perovskite-type oxides and combinations and multi-layers thereof.
In one example, following blanket deposition of the etch mask dielectric layer 65, which is shown in
The etch process described above exposes a portion 30 of the upper surface of the semiconductor substrate 5 that is adjacent to the second trench 15b. In one embodiment, the exposed portion 30 of the upper surface of the semiconductor substrate 5 has a length L2 ranging from 10 nm to 70 nm, as measured from the sidewall S1 of the second trench 15b. In another embodiment, the exposed portion 30 of the upper surface of the semiconductor substrate 5 has a length L2 ranging from 20 nm to 60 nm. In an even further embodiment, the exposed portion 30 of the upper surface of the semiconductor substrate 5 has a length L2 ranging from 30 nm to 40 nm, as measured from the sidewall Si of the second trench 15b.
In one embodiment, filling the first trench 15a and second trench 15b with a trench dielectric material 25 includes forming a portion of the trench dielectric material 25 atop the upper surface 30 of the semiconductor substrate 5 that is adjacent to the second trench 15b. In one embodiment, the trench dielectric material 25 is composed of a dielectric material, such as an oxide, polysilicon or a combination thereof. In one embodiment, the trench dielectric material 25 is deposited to fill the first trench 15a and the second trench 15b using chemical vapor deposition (CVD) or another like deposition process. The trench dielectric material 25 may optionally be densified after deposition.
In one embodiment, following filling the first trench 15a and the second trench 15b with the trench dielectric material 25, a planarization process may be used to provide a planar structure, in which the upper surface of the trench dielectric material 25 within the first trench 15a and the second trench 15b is coplanar with the first pad dielectric layer 10 of the pad stack 9.
The structure may then be processed to provide a microelectronic structure, in which each of the isolation regions 100a, 100b (first isolation region 100a, second isolation region 100b) provides for electrical isolation between adjacent devices, such as semiconductor devices, or components of electronic devices which require electrical isolation. In one embodiment, the portion 26 of the trench dielectric material 25 of the second isolation region 100b that is present on the exposed portion 30 of the upper surface of the semiconductor substrate 5, substantially reduces divot formation at the interface of the semiconductor substrate 5 and the trench dielectric material 25 within the trench 15. Typically, the portion 26 of the trench dielectric material 25 that is present atop the semiconductor substrate 5 has a length L3 that ranges from 1 nm to 70 nm, as measured from the sidewall Si of the second trench 15b, wherein in one example the length L3 may range from 20 nm to 30 nm.
It is noted that using the above method, the second isolation region 100b including the portion 26 of the trench dielectric material 25 that is present on the upper surface of the semiconductor substrate 5, which substantially reduces divot formation, may be incorporated with a first isolation region 100a that does not include the portion of the trench dielectric material that extends atop the surface of the semicondutor substrate 5. In addition to the second isolation regions 100b, which includes the portion 26 of the trench dielectric material 25 that extends atop the semiconductor surface 5 that reduces divot formation, a first isolation region 100a can be incorporated onto the same semiconductor surface 5 that does not include the extension of the trench dielectric material 25 to reduce divot formation. The impact of the divot varies by device type but for all device types there is reduced performance since the corner device, i.e, the device closest to the divot, is distinct from the channel device by 50% change in the threshold voltage. In addition, divot formation typically reduces the gate oxide reliability, in which the gate oxide can be thinned by the wet etch steps that are used in the multi-oxide processes that result in divot formation. These same factors may impact all device types especially when multiple gate oxides are patterned in sequence. The embodiments consistent with
Although in the present example the first pad dielectric layer is a thermally grown oxide, i.e., oxide pad dielectric layer 75, the first pad dielectric layer may be any dielectric material, in which examples include, but are not limited to: silicon oxide and silicon oxynitride. In one embodiment, the oxide pad dielectric layer 75 has a thickness ranging from 40 nm to 100 nm, wherein in one example the oxide pad dielectric is greater than 55 nm. The oxide pad dielectric layer 75 is formed using a thermal growth process, such as thermal oxidation. In one embodiment, thermal oxidation of the semiconductor substrate 5 is conducted using an oxygen containing atmosphere at a temperature greater than 700° C., wherein in one example the oxidation temperature may be greater than 850° C.
Still referring to
In one embodiment, forming the first etch mask 96 includes depositing a photoresist layer atop the oxide pad dielectric layer 75 and patterning the photoresist layer. Following the formation of the first etch mask 96, the exposed portion of the oxide pad dielectric layer 75 is removed using a selective etch process that includes an etch chemistry that is selective to the semiconductor substrate 5. In one embodiment, in which the oxide pad dielectric layer 75 is composed of silicon oxide and the semiconductor substrate 5 is composed of silicon, the etch chemistry may include hydrofluoric acid or CHF3/Ar/O2.
Following the formation of the gate dielectric 90, a trench isolation region 100 may be formed through the oxide pad dielectric layer 75 into the semiconductor substrate 5 that is abutting the active device region 101. In one embodiment, the step of forming the trench isolation region 100 extending through the oxide pad dielectric layer 75 into the portion of the semiconductor substrate 5 that is abutting the active device region 101 of the semiconductor substrate 5 may begin with depositing a second pad dielectric layer 76 atop the oxide pad dielectric layer 75 and the gate dielectric 90 in the via 80. The second pad dielectric layer 76 is typically a nitride containing material, such as silicon nitride, and may have a thickness greater than 100 nm, e.g., being 120 nm thick. The second pad dielectric layer 76 may be deposited using chemical vapor deposition, including but not limited to: plasma enhanced chemical vapor deposition (PECVD) and high density plasma chemical vapor deposition (HDPCVD). Following deposition, the second pad dielectric layer 76 may be planarized via chemical mechanical polishing (CMP).
Referring to
Trenches 15a, 15b may then be etched through the exposed portion of the second pad dielectric layer 76 through an underlying portion of the oxide pad dielectric layer 75 into a portion of the semiconductor substrate 5 that is abutting the active device region 101 of the semiconductor substrate 5. In one embodiment, the trenches 15a, 15b may be formed using an anisotropic etch process, such as reactive ion etch. In one embodiment, the etch chemistry that is selected to provide the trenches 15a, 15b is CH4, CHF3/O2, Ar/NF3.
Referring to
Referring to
In one embodiment, the method disclosed in
While preferred embodiments have been shown and described, various modifications and substitutions may be made thereto without departing from the spirit and scope of the invention. Accordingly, it is to be understood that the present invention has been described by way of illustration only, and such illustrations and embodiments as have been disclosed herein are not to be construed as limiting to the claims.
Claims
1. A method of forming an isolation region comprising:
- forming a first pad dielectric layer on an upper surface of a semiconductor substrate;
- forming a trench through the first pad dielectric layer into the semiconductor substrate;
- laterally etching the first pad dielectric layer to expose an upper surface of the semiconductor substrate adjacent the trench;
- filling the trench with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abutts the pad dielectric layer;
- removing the first pad dielectric layer to provide an exposed portion of the upper surface of the semiconductor substrate that is adjacent the trench dielectric material that extends atop the upper surface of the semiconductor substrate that is adjacent to the trench; and
- forming a conformal dielectric layer overlying the exposed portion of the semiconductor substrate and the first pad dielectric material.
2. The method of claim 1, wherein the first pad dielectric layer is composed of a nitride material.
3. The method of claim 2 further comprising a second pad dielectric layer composed of an oxide material present between the first pad dielectric layer and the semiconductor substrate.
4. The method of claim 1, wherein the trench dielectric material that is present in the trench and extends atop the upper surface of the semiconductor substrate that is adjacent to the trench is an oxide.
5. The method of claim 1 further comprising forming a dielectric liner on the upper surface of the semiconductor substrate that is adjacent to the trench prior to filling the trench with the trench dielectric material.
6. The method of claim 5, wherein the dielectric liner is composed of a thermally grown oxide.
7. The method of claim 1, wherein the laterally etching of the dielectric layer to expose the upper surface of the semiconductor substrate that is adjacent to the trench comprises a wet etch composed of hot phosphoric acid and hydrofluoric acid.
8. The method of claim 1, wherein the laterally etching removes a portion of the first pad dielectric layer that extends a dimension ranging from 10 nm to 70 nm as measured from a sidewall of the trench.
9. The method of claim 1, wherein the filling of the trench with the trench dielectric material includes high density plasma chemical vapor deposition followed by chemical mechanical planarization.
10. The method of claim 9, wherein following the filling of the trench with the trench dielectric material an upper surface of the trench dielectric material is treated with a etch process that comprises a hydrofluoric acid composition.
11. A method of forming an isolation region comprising:
- forming a pad dielectric stack on an upper surface of a semiconductor substrate, the pad stack including a first pad dielectric layer atop the semiconductor substrate and a second pad dielectric layer atop the first pad dielectric layer;
- forming at least a first trench and a second trench through the pad stack into the semiconductor substrate;
- forming an etch mask dielectric layer on a base and sidewall of the first trench and a portion of the pad stack adjacent the first trench;
- etching the pad stack using the etch mask dielectric layer as an etch mask to provide an exposed portion of the upper surface of the semiconductor substrate that is adjacent to the second trench in which the etch mask dielectric layer is not present; and
- filling the first trench and the second trench with a trench dielectric material, wherein a portion of the trench dielectric material is present on the exposed portion of the upper surface of the semiconductor substrate.
12. The method of claim 11, wherein the first pad dielectric layer is composed of an oxide material and the second pad dielectric layer is composed of a nitride material.
13. The method of claim 11, wherein the step of forming the etch mask dielectric layer on the base and the sidewall of the first trench and the portion of the pad dielectric stack adjacent the first trench comprises: depositing a blanket conformal dielectric layer atop the pad dielectric stack, the first trench, and the second trench; forming an etch mask on the portion of the blanket conformal dielectric layer overlying the portion blanket conformal dielectric layer on the base and the sidewall of the first trench and the portion of the pad dielectric stack adjacent the first trench; and removing exposed portions of the blanket conformal dielectric layer.
14. The method of claim 11, wherein the etching of the pad dielectric stack using the etch mask dielectric layer as the etch mask to provide the exposed portion of the upper surface of the semiconductor substrate that is adjacent to the second trench includes a first etch step for removing at least a portion of the first pad dielectric layer selective to the second pad dielectric layer and a second etch step for removing the second pad dielectric layer selective to the semiconductor substrate.
15. The method of claim 14, wherein the second etch step removes the etch mask dielectric layer.
16. The method of claim 11, wherein a remaining portion of the first pad dielectric layer provides an etch mask for the second etch step that produces an exposed portion of the upper surface of the semiconductor substrate that is adjacent the second trench that extends a dimension ranging from 10 nm to 70 nm, as measured from a sidewall of the second trench.
17. The method of claim 11, wherein the step of the filling of the first trench and the second trench with the trench dielectric material, wherein the portion of the trench dielectric material is present on the exposed portion of the upper surface of the semiconductor substrate comprises depositing an oxide and planarizing until an upper surface of the trench dielectric material that is present in the first trench and the second trench is coplanar with an upper surface of a remaining portion of the pad stack.
18. The method of claim 17, wherein following the step of the filling of the first trench and the second trench with the trench dielectric material the remaining portion of the pad stack is removed.
19. The method of claim 11, wherein the trench dielectric material that is present in the second trench forms an isolation region having an upper portion with a first width and a lower portion with a second width, wherein the first width is greater than the second width.
20. The method of claim 19, wherein the first width ranges from 1 nm to 10 nm, and the second width ranges from 10 nm to 70 nm.
21. A method of forming an isolation region comprising:
- thermally growing a first pad dielectric layer on a semiconductor substrate, wherein the first pad dielectric layer has a thickness greater than 40 nm;
- removing a portion of the first pad dielectric layer to provide a via to an exposed surface of the semiconductor substrate that is overlying at least a portion of the active device region of the semiconductor substrate;
- forming a gate dielectric on the exposed surface of the semiconductor substrate; and
- forming a trench isolation region extending through the first pad dielectric layer into a portion of the semiconductor substrate that is abutting the active device region of the semiconductor substrate.
22. The method of claim 21, wherein the semiconductor substrate comprises a sacraficial oxide formed thereon.
23. The method of claim 21, wherein the step of thermally growing the first pad dielectric layer on the semiconductor substrate comprises thermal oxidation at a temperature greater than 700° C.
24. The method of claim 21, wherein the step of the removing of the portion of the first pad dielectric layer to provide the via to the exposed surface of the semiconductor substrate that is overlying the at least the portion of the active device region of the semiconductor substrate includes forming a forming an etch mask atop the first pad dielectric layer that exposes a portion of the first pad dielectric layer overlying the active device region and etching the portion of the first pad dielectric layer selective to the exposed surface of the semiconductor substrate.
25. The method of claim 21, wherein forming the etch mask includes depositing a photoresist layer atop the first pad dielectric layer and patterning the photoresist layer.
26. The method of claim 21, wherein the forming of the gate dielectric on the exposed surface of the semiconductor substrate comprises thermal oxidation.
27. The method of claim 21, wherein the gate dielectric has a thickness ranging from 2 nm to 5 nm.
28. The method of claim 21, wherein the step of forming the trench isolation region extending through the first pad dielectric layer into the portion of the semiconductor substrate that is abutting the active device region of the semiconductor substrate includes:
- depositing a second pad dielectric layer atop the first pad dielectric layer including the gate dielectric in the via;
- forming an etch mask atop the second pad dielectic layer to provide an exposed portion of the second pad dielectric layer overlying the portion of the semiconductor substrate that is abutting the active device region of the semiconductor substrate;
- etching a trench through the exposed portion of the second pad dielectric layer through an underlying portion of the first pad dielectric layer into a portion of the semiconductor substrate that is subtting the active device region of the semiconductor substrate;
- laterally etching at least the first pad dielectric layer to expose an upper surface of the semiconductor substrate adjacent the trench; and
- filling the trench with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abutts the first pad dielectric layer.
29. The method of claim 28, wherein the first pad dielectric layer comprises an oxide, the second pad dielectric layer comprises a nitride, and the trench dielectric material comprises an oxide.
30. The method of claim 28, wherein following the step of filling the trench with the trench dielectric material, the trench dielectric material is planarized to have an upper surface substantially coplanar with the upper surface of the second pad dielectric layer.
31. The method of claim 30, further comprising recessing the upper surface of the trench dielectric material relative to the upper surface of the second pad dielectric layer, and removing the second pad dielectric layer.
32. The method of claim 31, further comprising implanting an n-type or p-type dopant into the semiconducting substrate underlying the gate dielectric, and forming a gate conductor atop the gate dielectric.
Type: Application
Filed: Nov 19, 2009
Publication Date: May 19, 2011
Patent Grant number: 8227318
Applicant:
Inventors: Max Levy (Essex Junction, NY), Natalie Feilchenfeld (Essex Junction, NY), Richard Phelps (Essex Junction, NY), BethAnn Rainey (Essex Junction, NY), James Slinkman (Essex Junction, NY), Steven H. Voldman (Essex Junction, NY), Michael Zierak (Essex Junction, NY), Hubert Enichlmair (Graz), Martin Knaipp (Unterpremstaetten), Bernhard Loeffler (Gleisdorf), Rainer Minixhofer (Unterpremstaetten), Jong-Mun Park (Graz), Georg Roehrer (Graz)
Application Number: 12/622,028
International Classification: H01L 21/762 (20060101); H01L 21/336 (20060101);