Patents by Inventor Beth Cook

Beth Cook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CAPPED ELECTRODE CONTACT FOR RRAM CELLS AND MEMORY CELL ARRAYS
    Publication number: 20170271587
    Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricated a memory cell comprising depositing a material to form an interface cap above a bulk conductive plug and below active cell materials in the memory cell.
    Type: Application
    Filed: June 8, 2017
    Publication date: September 21, 2017
    Inventors: Scott Sills, Beth Cook, Nirmal Ramaswamy
  • Interfacial cap for electrode contacts in memory cell arrays
    Patent number: 9691976
    Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricated a memory cell comprising depositing a material to form an interface cap above a bulk conductive plug and below active cell materials in the memory cell.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: June 27, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Scott Sills, Beth Cook, Nirmal Ramaswamy
  • INTERFACIAL CAP FOR ELECTRODE CONTACTS IN MEMORY CELL ARRAYS
    Publication number: 20160181519
    Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricated a memory cell comprising depositing a material to form an interface cap above a bulk conductive plug and below active cell materials in the memory cell.
    Type: Application
    Filed: March 3, 2016
    Publication date: June 23, 2016
    Inventors: Scott Sills, Beth Cook, Nirmal Ramaswamy
  • RESISTIVE MEMORY WITH A THERMALLY INSULATING REGION
    Publication number: 20160104840
    Abstract: A resistive memory includes a memory cell having a first electrode, a second electrode and a resistive memory element between the first electrode and the second electrode. The memory cell includes a thermally insulating region. The thermally insulating region may be included in at least one electrode of the memory cell and/or within an electrically insulating region. The thermally insulating region can confine heat within the memory cell and thereby can reduce the current and/or voltage needed to write information in the resistive memory element.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 14, 2016
    Inventors: Beth Cook, Nirmal Ramaswamy, Shuichiro Yasuda, Scott Sills, Koji Miyata
  • Interfacial cap for electrode contacts in memory cell arrays
    Patent number: 9306162
    Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricated a memory cell comprising depositing a material to form an interface cap above a bulk conductive plug and below active cell materials in the memory cell.
    Type: Grant
    Filed: January 4, 2014
    Date of Patent: April 5, 2016
    Assignee: Sony Corporation
    Inventors: Scott Sills, Beth Cook, Nirmal Ramaswamy
  • INTERFACIAL CAP FOR ELECTRODE CONTACTS IN MEMORY CELL ARRAYS
    Publication number: 20150194601
    Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricated a memory cell comprising depositing a material to form an interface cap above a bulk conductive plug and below active cell materials in the memory cell.
    Type: Application
    Filed: January 4, 2014
    Publication date: July 9, 2015
    Applicant: Sony Corporation
    Inventors: Scott Sills, Beth Cook, Nirmal Ramaswamy
  • INTEGRATED CIRCUIT SYSTEM WITH NON-VOLATILE MEMORY AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20140306172
    Abstract: An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die having an address switch; a bottom electrode contact, free of halogen constituents, characteristic of a chemical vapor deposition or an atomic layer deposition, and coupled to the address switch; a transition material layer directly on the bottom electrode contact; and a top electrode contact, directly on the transition material layer, for forming a non-volatile memory array on the integrated circuit die.
    Type: Application
    Filed: April 12, 2013
    Publication date: October 16, 2014
    Applicant: Sony Corporation
    Inventors: Scott Sills, Muralikrishnan Balakrishnan, Beth Cook, Durai Vishak Nirmal Ramaswamy, Shuichiro Yasuda