Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region.

Abstract: Techniques for reading from and/or writing to a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first memory cell array having a first plurality of memory cells arranged in a matrix of rows and columns and a second memory cell array having a second plurality of memory cells arranged in a matrix of row and columns. The apparatus may also include a data sense amplifier latch circuitry having a first input node and a second input node. The apparatus may further include a first bit line input circuitry configured to couple the first memory cell array to the first input node of the data sense amplifier latch circuitry and a second bit line input circuitry configured to couple the second memory cell array to the second input node of the data sense amplifier latch circuitry.

Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region.

Abstract: A signal line 12 has at a first location a first driver 14 to drive a first signal level on that signal line 12. A second driver 16 is provided at a second location, separated from the first location, and serves to drive the line signal to a different value from that driven by the first driver 14. Associated with each of these drivers 14, 16 are respective keeper circuits 18, 20, 22; 24, 26, 28 serving to maintain the signal value driven by the respective remote driver 16; 14. Thus, the first keeper 18, 20, 22 local to the first driver 14 serves to maintain the signal value driven by the second driver 16. The keepers 18, 20, 22; 24, 26, 28 are disabled by the control signal which enables their local driver 14; 16 and thus do not contend with the change being driven by their local driver 14, 16.

Abstract: Techniques for providing a source line plane are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for providing a source line plane. The apparatus may comprise a source line plane coupled to at least one constant voltage source. The apparatus may also comprise a plurality of memory cells arranged in an array of rows and columns, each memory cell including one or more memory transistors. Each of the one or more memory transistors may comprise a first region coupled to the source line plane, a second region coupled to a bit line, a body region disposed between the first region and the second region, wherein the body region may be electrically floating, and a gate coupled to a word line and spaced apart from, and capacitively coupled to, the body region.

Abstract: A semiconductor memory storage cell and a memory comprising an array of these storage cells is disclosed. The storage cell comprising: a feedback loop comprising two devices for storing opposite binary values; data input and output for inputting data to and outputting data from said two devices; and each of said two devices comprising a power source input, such that each device can be powered independently of the other.

Abstract: A semiconductor memory storage cell and a memory comprising an array of these storage cells is disclosed. The storage cell comprising: a feedback loop comprising two devices for storing opposite binary values; data input and output for inputting data to and outputting data from said two devices; and each of said two devices comprising a power source input, such that each device can be powered independently of the other.

Abstract: An integrated circuit 18 includes a memory 20 having timing circuitry formed of a global controller 26 and a self-timing path for triggering the sense amplifiers 28 to read bit lines 30 within the array of bit cells 24. The self timing path includes timing cells 34 embedded within the array 24 and modelling behavior of the bit cells 32 in changing the bit line signals. The self timing path uses active low signalling throughout as this can be implemented with predominantly n-type transistors matching the n-type transistors which dominate within the array 24.

Abstract: An integrated circuit 18 includes a memory 20 having timing circuitry formed of a global controller 26 and a self-timing path for triggering the sense amplifiers 28 to read bit lines 30 within the array of bit cells 24. The self timing path includes timing cells 34 embedded within the array 24 and modelling behaviour of the bit cells 32 in changing the bit line signals. The self timing path uses active low signalling throughout as this can be implemented with predominantly n-type transistors matching the n-type transistors which dominate within the array 24.

Abstract: A signal line 12 has at a first location a first driver 14 to drive a first signal level on that signal line 12. A second driver 16 is provided at a second location, separated from the first location, and serves to drive the line signal to a different value from that driven by the first driver 14. Associated with each of these drivers 14, 16 are respective keeper circuits 18, 20, 22; 24, 26, 28 serving to maintain the signal value driven by the respective remote driver 16; 14. Thus, the first keeper 18, 20, 22 local to the first driver 14 serves to maintain the signal value driven by the second driver 16. The keepers 18, 20, 22; 24, 26, 28 are disabled by the control signal which enables their local driver 14; 16 and thus do not contend with the change being driven by their local driver 14, 16.

Abstract: A Static Random Access Memory (SRAM) dual port memory with an improved core cell design having internally matched capacitances and decreased bit line capacitance is disclosed. The core cell is fabricated on a substrate divided into three approximately equal columns of different substrate materials. In a preferred embodiment, the memory cell is fabricated on a central p-type column that in turn is sandwiched between two n-type columns. The three-column substrate architecture permits reduced bit line height, with an accompanying reduction in bit line capacitance, which increases the speed at which the core cell can operate. The architecture also permits separating the core cell's bitline and complement bitline, reducing capacitive coupling between these lines and increasing the core cell's operating speed. The architecture further permits better matching of internal node capacitances.

Abstract: A Static Random Access Memory (SRAM) dual port memory with an improved core cell design having internally matched capacitances and decreased bit line capacitance is disclosed. The core cell is fabricated on a substrate divided into three approximately equal columns of different substrate materials. In a preferred embodiment, the memory cell is fabricated on a central p-type column that in turn is sandwiched between two n-type columns. The three-column substrate architecture permits reduced bit line height, with an accompanying reduction in bit line capacitance, which increases the speed at which the core cell can operate. The architecture also permits separating the core cell's bitline and complement bitline, reducing capacitive coupling between these lines and increasing the core cell's operating speed. The architecture further permits better matching of internal node capacitances.

Abstract: A load independent single ended sense amplifier is provided. The sense amplifier includes a first current mirror having a first load transistor and a first reflected current transistor, and a second current mirror having a second load transistor and a second reflected current transistor. The first load transistor is capable of communicating a load current to the second load transistor. In addition, a reflected current flowing through the first reflected current transistor and the second reflected current transistor generates an amplified load current.