Abstract: A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission.

Abstract: A frequency mixing apparatus is provided. In the frequency mixing apparatus, a PMOS transistor is coupled to an NMOS transistor in a cascode configuration and an LO signal is applied to the bulks of the PMOS and NMOS transistors so that an input signal applied to their gates is mixed with the LO signal. High isolation between the bulks and gates of the transistors resulting from application of the LO signal to the bulks prevents leakage of the LO signal, thereby decreasing a DC offset voltage. This renders the frequency mixing applicable to a DCR. Also, due to the cascade configuration similar to an inverter configuration, the frequency mixing apparatus can be incorporated in an FPGA of a MODEM in SDR applications. Frequency mixing based on switching of a threshold voltage decreases a noise factor and enables frequency mixing in a low supply voltage range, thereby decreasing power consumption.