Abstract: Surface pretreatment of SiGe or Ge surfaces prior to gate oxide deposition cleans the SiGe or Ge surface to provide a hydrogen terminated surface or a sulfur passivated (or S—H) surface. Atomic layer deposition (ALD) of a high-dielectric-constant oxide at a low temperature is conducted in the range of 25-200° C. to form an oxide layer. Annealing is conducted at an elevated temperature. A method for oxide deposition on a damage sensitive III-V semiconductor surface conducts in-situ cleaning of the surface with cyclic pulsing of hydrogen and TMA (trimethyl aluminum) at a low temperature in the range of 100-200° C. Atomic layer deposition (ALD) of a high-dielectric-constant oxide forms an oxide layer. Annealing is conducted at an elevated temperature. The annealing can create a silicon terminated interfaces.

Abstract: A system and method for simulating behavior of a spin transfer torque magnetic random access memory (STT-MRAM) device includes a hardware processor (HP) and logic instructions (LI) stored in memory. The LI are executed by the HP to configure a library of functional blocks (FBs) to capture physical phenomenon of at least one element of the STT-MRAM configured in the form of a magnetic stack. Selected elements of the stack are mapped into a set of selected FBs (SFBs). The mapping converts the stack to a spin device circuit (SDC) represented by the SFBs. The SFBs are assembled to form the SDC replicating the stack. The SDC includes an electron spin transport, a magnet-dynamics, a magnetic coupling and a coupled electron transport+magnet-dynamics FBs. A set of output parameters simulating the STT-MRAM is generated by the SFBs in response to receiving a set of input parameters.

Abstract: A system and method for simulating behavior of a spin transfer torque magnetic random access memory (STT-MRAM) device includes a hardware processor (HP) and logic instructions (LI) stored in memory. The LI are executed by the HP to configure a library of functional blocks (FBs) to capture physical phenomenon of at least one element of the STT-MRAM configured in the form of a magnetic stack. Selected elements of the stack are mapped into a set of selected FBs (SFBs). The mapping converts the stack to a spin device circuit (SDC) represented by the SFBs. The SFBs are assembled to form the SDC replicating the stack. The SDC includes an electron spin transport, a magnet-dynamics, a magnetic coupling and a coupled electron transport+magnet-dynamics FBs. A set of output parameters simulating the STT-MRAM is generated by the SFBs in response to receiving a set of input parameters.

Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.

Abstract: Surface pretreatment of SiGe or Ge surfaces prior to gate oxide deposition cleans the SiGe or Ge surface to provide a hydrogen terminated surface or a sulfur passivated (or S—H) surface. Atomic layer deposition (ALD) of a high-dielectric-constant oxide at a low temperature is conducted in the range of 25-200° C. to form an oxide layer. Annealing is conducted at an elevated temperature. A method for oxide deposition on a damage sensitive III_V semiconductor surface conducts in-situ cleaning of the surface with cyclic pulsing of hydrogen and TMA (trimethyl aluminum) at a low temperature in the range of 100-200° C. Atomic layer deposition (ALD) of a high-dielectric-constant oxide forms an oxide layer. Annealing is conducted at an elevated temperature. The annealing can create a silicon terminated interfaces.

Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.

Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.

Abstract: Approaches for providing asymmetrical channel growth of a cladding layer over fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, in one approach, a FinFET device comprises a set of fins formed from a substrate, a shallow trench isolation layer formed adjacent each of the set of fins, and a cladding layer (e.g., silicon germanium) formed over each of the set of fins, wherein a thickness of the cladding layer atop each of the set of fins is greater than a thickness of the cladding layer along each sidewall of the set of fins. In one embodiment, the thickness of the cladding layer atop the set of fins is approximately two times (2×) greater than the thickness of the cladding layer along each sidewall of the set of fins.

Abstract: One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode.

Abstract: One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode.

Abstract: One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode.