ALTERNATIVE GATE DIELECTRIC FILMS FOR SILICON GERMANIUM AND GERMANIUM CHANNEL MATERIALS
Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.
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The present invention relates generally to semiconductor fabrication, and more particularly, to gate dielectric films for silicon germanium and germanium channel materials.
BACKGROUNDAs technology dimensions scale for semiconductor integrated circuits (ICs), new challenges are being created with regards to metal-oxide semiconductor field-effect transistors (MOSFETs). Silicon germanium and germanium channel materials are being introduced due to higher mobility (electrons and holes) when compared to conventional Si devices. In order to continuously scale devices, maintaining equivalent oxide thickness (EOT) and gate leakage are needed to meet stringent requirements. In addition to channel materials, scaling further requires gate dielectric materials with higher k values. It is therefore desirable to have improvements in dielectric films and methods of fabrication.
SUMMARYEmbodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL). Therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer providing a reduced effective oxide thickness (EOT), resulting in improved device performance.
In a first aspect, embodiments of the present invention provide a method of forming a semiconductor structure, comprising: performing a surface oxidation of a semiconductor substrate to form an interfacial oxide layer; depositing a first dielectric layer on the interfacial oxide layer; and depositing a second dielectric layer on the first dielectric layer.
In a second aspect, embodiments of the present invention provide a semiconductor structure comprising: a silicon germanium substrate comprising an oxidized top surface; a first dielectric layer disposed on the oxidized top surface of the silicon germanium substrate; and a second dielectric layer disposed on the first dielectric layer.
In a third aspect, embodiments of the present invention provide a semiconductor structure comprising: a semiconductor substrate; a transistor gate disposed on the semiconductor substrate; a gate dielectric disposed between the semiconductor substrate and the transistor gate, wherein the gate dielectric comprises an oxidized surface region of the semiconductor substrate, an aluminum oxide layer disposed on the oxidized surface region, and a high-K dielectric layer disposed on the aluminum oxide layer.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the present teachings and, together with the description, serve to explain the principles of the present teachings.
Certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. The cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a “true” cross-sectional view, for illustrative clarity.
Often, similar elements may be referred to by similar numbers in various figures (FIGs) of the drawing, in which case typically the last two significant digits may be the same, the most significant digit being the number of the drawing figure (FIG). Furthermore, for clarity, some reference numbers may be omitted in certain drawings.
It will be appreciated that this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. For example, as used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Reference throughout this specification to one “embodiment,” “an embodiment,” “embodiments,” “exemplary embodiments,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” “in embodiments” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
The terms “overlying” or “atop”, “positioned on” or “positioned atop”, “underlying”, “beneath” or “below” mean that a first element, such as a first structure (e.g., a first layer), is present on a second element, such as a second structure (e.g., a second layer), wherein intervening elements, such as an interface structure (e.g., interface layer), may be present between the first element and the second element.
While the invention has been particularly shown and described in conjunction with exemplary embodiments, it will be appreciated that variations and modifications will occur to those skilled in the art. For example, although the illustrative embodiments are described herein as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events unless specifically stated. Some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the invention.
Claims
1.-12. (canceled)
13. A semiconductor structure comprising:
- a silicon germanium substrate comprising an oxidized top surface;
- a first dielectric layer disposed on the oxidized top surface of the silicon germanium substrate; and
- a second dielectric layer disposed on the first dielectric layer.
14. The semiconductor structure of claim 13, wherein the first dielectric layer comprises aluminum oxide and lanthanum oxide.
15. The semiconductor structure of claim 14, wherein the second dielectric layer comprises titanium oxide.
16. The semiconductor structure of claim 14, wherein the second dielectric layer comprises lanthanum oxide.
17. The semiconductor structure of claim 14, wherein the second dielectric layer comprises zirconium oxide.
18. A semiconductor structure comprising:
- a semiconductor substrate;
- a transistor gate disposed on the semiconductor substrate;
- a gate dielectric disposed between the semiconductor substrate and the transistor gate, wherein the gate dielectric comprises an oxidized surface region of the semiconductor substrate, an aluminum oxide layer disposed on the oxidized surface region, and a high-K dielectric layer disposed on the aluminum oxide layer.
19. The semiconductor structure of claim 18, wherein the high-K dielectric layer comprises a titanium oxide layer.
20. The semiconductor structure of claim 18, wherein the high-K dielectric layer comprises zirconium oxide.
21. A semiconductor structure comprising:
- a semiconductor substrate comprising an oxidized top surface;
- a first dielectric layer disposed on the oxidized top surface of the semiconductor substrate; and
- a second dielectric layer disposed on the first dielectric layer.
22. The semiconductor structure of claim 21, wherein the first dielectric layer comprises aluminum oxide and lanthanum oxide.
23. The semiconductor structure of claim 22, wherein the second dielectric layer comprises titanium oxide.
24. The semiconductor structure of claim 22, wherein the second dielectric layer comprises lanthanum oxide.
25. The semiconductor structure of claim 22, wherein the second dielectric layer comprises zirconium oxide.
26. The semiconductor structure of claim 13, wherein the oxidized top surface has a thickness ranging from about 2 angstroms to about 5 angstroms.
27. The semiconductor structure of claim 18, wherein the oxidized surface region has a thickness ranging from about 2 angstroms to about 5 angstroms.
28. The semiconductor structure of claim 21, wherein the oxidized top surface has a thickness ranging from about 2 angstroms to about 5 angstroms.
Type: Application
Filed: Jan 14, 2016
Publication Date: May 12, 2016
Applicant: GLOBALFOUNDRIES INC. (Grand Cayman)
Inventors: Shariq Siddiqui (Albany, NY), Bhagawan Sahu (Watervliet, NY), Rohit Galatage (Clifton Park, NY), Hoon Kim (Clifton Park, NY)
Application Number: 14/995,956