Patents by Inventor Bhaskar Kumar

Bhaskar Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180294146
    Abstract: Implementations of the present disclosure generally relate to an apparatus for reducing particle contamination on substrates in a plasma processing chamber. The apparatus for reduced particle contamination includes a chamber body, a lid coupled to the chamber body. The chamber body and the lid define a processing volume therebetween. The apparatus also includes a substrate support disposed in the processing volume and an edge ring. The edge ring includes an inner lip disposed over a substrate, a top surface connected to the inner lip, a bottom surface opposite the top surface and extending radially outward from the substrate support, and an inner step between the bottom surface and the inner lip. To avoid depositing the particles on the substrate being processed when the plasma is de-energized, the edge ring shifts the high plasma density zone away from the edge area of the substrate.
    Type: Application
    Filed: April 6, 2018
    Publication date: October 11, 2018
    Inventors: Bhaskar KUMAR, Prashanth KOTHNUR, Sidharth BHATIA, Anup Kumar SINGH, Vivek Bharat SHAH, Ganesh BALASUBRAMANIAN, Changgong WANG
  • Publication number: 20180261500
    Abstract: Methods of discouraging poreseal deposition on metal (e.g. copper) at the bottom of a via during a poresealing process are described. A self-assembled monolayer (SAM) is selectively formed on the exposed metal surface and prevents or discourages formation of poreseal on the metal. The SAM is selectively formed by exposing a patterned substrate to a SAM molecule which preferentially binds to exposed metal surfaces rather than exposed dielectric surfaces. The selected SAM molecules tend to not bind to low-k films. The SAM and SAM molecule are also chosen so the SAM tolerates subsequent processing at relatively high processing temperatures above 140° C. or 160° C. Aliphatic or aromatic SAM molecules with thiol head moieties may be used to form the SAM.
    Type: Application
    Filed: March 7, 2017
    Publication date: September 13, 2018
    Inventors: Geetika Bajaj, Tapash Chakraborty, Prerna Sonthalia Goradia, Robert Jan Visser, Bhaskar Kumar, Deenesh Padhi
  • Patent number: 10074559
    Abstract: Methods of discouraging poreseal deposition on metal (e.g. copper) at the bottom of a via during a poresealing process are described. A self-assembled monolayer (SAM) is selectively formed on the exposed metal surface and prevents or discourages formation of poreseal on the metal. The SAM is selectively formed by exposing a patterned substrate to a SAM molecule which preferentially binds to exposed metal surfaces rather than exposed dielectric surfaces. The selected SAM molecules tend to not bind to low-k films. The SAM and SAM molecule are also chosen so the SAM tolerates subsequent processing at relatively high processing temperatures above 140° C. or 160° C. Aliphatic or aromatic SAM molecules with thiol head moieties may be used to form the SAM.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: September 11, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Geetika Bajaj, Tapash Chakraborty, Prerna Sonthalia Goradia, Robert Jan Visser, Bhaskar Kumar, Deenesh Padhi
  • Publication number: 20180204750
    Abstract: Embodiments of the present disclosure relate to a method and an apparatus for monitoring plasma behavior inside a plasma processing chamber. In one example, a method for monitoring plasma behavior includes acquiring at least one image of a plasma, and determining a plasma parameter based on the at least one image.
    Type: Application
    Filed: January 18, 2018
    Publication date: July 19, 2018
    Inventors: Sidharth BHATIA, Edward P. HAMMOND, IV, Bhaskar KUMAR, Anup Kumar SINGH, Vivek Bharat SHAH, Ganesh BALASUBRAMANIAN
  • Publication number: 20180114679
    Abstract: Implementations of the present disclosure provide methods for treating a processing chamber. In one implementation, the method includes purging a 300 mm substrate processing chamber, without the presence of a substrate, by flowing a purging gas into the substrate processing chamber at a flow rate of about 0.14 sccm/mm2 to about 0.33 sccm/mm2 and a chamber pressure of about 1 Torr to about 30 Torr, with a throttle valve of a vacuum pump system of the substrate processing chamber in a fully opened position, wherein the purging gas is chemically reactive with deposition residue on exposed surfaces of the substrate processing chamber.
    Type: Application
    Filed: September 28, 2017
    Publication date: April 26, 2018
    Inventors: Vivek Bharat SHAH, Bhaskar KUMAR, Ganesh BALASUBRAMANIAN
  • Publication number: 20180036775
    Abstract: Implementations described herein generally relate to methods and apparatus for in-situ removal of unwanted deposition buildup from one or more interior surfaces of a semiconductor substrate-processing chamber. In one implementation, the method comprises forming a reactive fluorine species from a fluorine-containing cleaning gas mixture. The method further comprises delivering the reactive fluorine species into a processing volume of a substrate-processing chamber. The processing volume includes one or more aluminum-containing interior surfaces having unwanted deposits formed thereon. The method further comprises permitting the reactive fluorine species to react with the unwanted deposits and aluminum-containing interior surfaces of the substrate-processing chamber to form aluminum fluoride. The method further comprises exposing nitrogen-containing cleaning gas mixture to in-situ plasma to form reactive nitrogen species in the processing volume.
    Type: Application
    Filed: July 19, 2017
    Publication date: February 8, 2018
    Inventors: Vivek Bharat SHAH, Anup Kumar SINGH, Bhaskar KUMAR, Ganesh BALASUBRAMANIAN, Bok Hoen KIM
  • Patent number: 9793108
    Abstract: A method for sealing porous low-k dielectric films is provided. The method comprises exposing a substrate to UV radiation and a first reactive gas, wherein the substrate has an open feature defined therein, the open feature defined by a porous low-k dielectric layer and a conductive material, wherein the porous low-k dielectric layer is a silicon and carbon containing material and selectively forming a pore sealing layer in the open feature on exposed surfaces of the porous low-k dielectric layer using UV assisted photochemical vapor deposition.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: October 17, 2017
    Assignee: APPLIED MATERIAL, INC.
    Inventors: He Ren, Mehul B. Naik, Deenesh Padhi, Priyanka Dash, Bhaskar Kumar, Alexandros T. Demos
  • Patent number: 9780223
    Abstract: Embodiments of the invention provide a method of forming a group III-V material utilized in thin film transistor devices. In one embodiment, a gallium arsenide based (GaAs) layer with or without dopants formed from a solution based precursor may be utilized in thin film transistor devices. The gallium arsenide based (GaAs) layer formed from the solution based precursor may be incorporated in thin film transistor devices to improve device performance and device speed. In one embodiment, a thin film transistor structure includes a gate insulator layer disposed on a substrate, a GaAs based layer disposed over the gate insulator layer, and a source-drain metal electrode layer disposed adjacent to the GaAs based layer.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: October 3, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kaushal K. Singh, Robert Jan Visser, Bhaskar Kumar
  • Patent number: 9646876
    Abstract: A method of forming features in a dielectric layer is described. A via, trench or a dual-damascene structure may be present in the dielectric layer prior to depositing a conformal aluminum nitride layer. The conformal aluminum nitride layer is configured to serve as a barrier to prevent diffusion across the barrier. The methods of forming the aluminum nitride layer involve the alternating exposure to two precursor treatments (like ALD) to achieve high conformality. The high conformality of the aluminum nitride barrier layer enables the thickness to be reduced and the effective conductivity of the subsequent gapfill metal layer to be increased.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: May 9, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Deenesh Padhi, Srinivas Guggilla, Alexandros T. Demos, Bhaskar Kumar, He Ren, Priyanka Dash
  • Publication number: 20160379819
    Abstract: A method for sealing porous low-k dielectric films is provided. The method comprises exposing a substrate to UV radiation and a first reactive gas, wherein the substrate has an open feature defined therein, the open feature defined by a porous low-k dielectric layer and a conductive material, wherein the porous low-k dielectric layer is a silicon and carbon containing material and selectively forming a pore sealing layer in the open feature on exposed surfaces of the porous low-k dielectric layer using UV assisted photochemical vapor deposition.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: He REN, Mehul B. NAIK, Deenesh PADHI, Priyanka DASH, Bhaskar KUMAR, Alexandros T. DEMOS
  • Publication number: 20160322509
    Abstract: Embodiments of the invention provide a method of forming a group III-V material utilized in thin film transistor devices. In one embodiment, a gallium arsenide based (GaAs) layer with or without dopants formed from a solution based precursor may be utilized in thin film transistor devices. The gallium arsenide based (GaAs) layer formed from the solution based precursor may be incorporated in thin film transistor devices to improve device performance and device speed. In one embodiment, a thin film transistor structure includes a gate insulator layer disposed on a substrate, a GaAs based layer disposed over the gate insulator layer, and a source-drain metal electrode layer disposed adjacent to the GaAs based layer.
    Type: Application
    Filed: July 14, 2016
    Publication date: November 3, 2016
    Inventors: Kaushal K. SINGH, Robert Jan VISSER, Bhaskar KUMAR
  • Publication number: 20160254181
    Abstract: A method of forming features in a dielectric layer is described. A via, trench or a dual-damascene structure may be present in the dielectric layer prior to depositing a conformal aluminum nitride layer. The conformal aluminum nitride layer is configured to serve as a barrier to prevent diffusion across the barrier. The methods of forming the aluminum nitride layer involve the alternating exposure to two precursor treatments (like ALD) to achieve high conformality. The high conformality of the aluminum nitride barrier layer enables the thickness to be reduced and the effective conductivity of the subsequent gapfill metal layer to be increased.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 1, 2016
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Deenesh Padhi, Srinivas Guggilla, Alexandros T. Demos, Bhaskar Kumar, He Ren, Priyanka Dash
  • Publication number: 20160172238
    Abstract: A method of forming features in a low-k dielectric layer is described. A via, trench or a dual damascene structure may be present in the low-k dielectric layer prior to depositing a conformal hermetic layer. The conformal hermetic layer is configured to keep water and contaminants out. Some of the same conformal hermetic layer may deposit on the underlying copper. The portion of the conformal hermetic layer on the underlying copper is preferentially removed but the beneficial portion on the low-k dielectric layer remains. The selective removal of the conformal hermetic layer may be accomplished using a dry etch or a wet etch using a weak organic acid.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 16, 2016
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Bhaskar Kumar, Deenesh Padhi, Alexandros T. Demos, Tapash Chakraborty, Geetika Bajaj, Robert Jan Visser
  • Patent number: 9252392
    Abstract: A method and apparatus for depositing a multilayer barrier structure is disclosed herein. In one embodiment, a thin barrier layer formed over an organic semiconductor includes a non-conformal organic layer, an inorganic layer formed over the non-conformal organic layer, a metallic layer formed over the inorganic layer and a second organic layer formed over the metallic layer. In another embodiment, a method of depositing a barrier layer includes forming an organic semiconductor device over the exposed surface of a substrate, depositing an inorganic layer using CVD, depositing a metallic layer comprising one or more metal oxide or metal nitride layers over the inorganic layer by ALD, each of the metal oxide or metal nitride layers comprising a metal, wherein the metal is selected from the group consisting of aluminum, hafnium, titanium, zirconium, silicon or combinations thereof and depositing an organic layer over the metallic layer.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: February 2, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bhaskar Kumar, Dieter Haas
  • Patent number: 8895842
    Abstract: A method and apparatus for forming solar cells is provided. In one embodiment, a photovoltaic device includes a first TCO layer disposed on a substrate, a second TCO layer disposed on the first TCO layer, and a p-type silicon containing layer formed on the second TCO layer. In another embodiment, a method of forming a photovoltaic device includes forming a first TCO layer on a substrate, forming a second TCO layer on the first TCO layer, and forming a first p-i-n junction on the second TCO layer.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: November 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Shuran Sheng, Yong Kee Chae, Stefan Klein, Amir Al-Bayati, Bhaskar Kumar
  • Patent number: 8846437
    Abstract: Embodiments of the invention provide a method of forming a doped gallium arsenide based (GaAs) layer from a solution based precursor. The doped gallium arsenide based (GaAs) layer formed from the solution based precursor may assist solar cell devices to improve light absorption and conversion efficiency. In one embodiment, a method of forming a solar cell device includes forming a first layer with a first type of dopants doped therein over a surface of a substrate, forming a GaAs based layer on the first layer, and forming a second layer with a second type of dopants doped therein on the GaAs based layer.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: September 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Kaushal K. Singh, Robert Jan Visser, Srikant Rao, Bhaskar Kumar, Claire J. Carmalt, Ranga Rao Arnepalli, Omkaram Nalamasu, Gaurav Saraf, Sanjayan Sathasivam, Christopher Stuart Blackman
  • Publication number: 20140264297
    Abstract: A method and apparatus for depositing a multilayer barrier structure is disclosed herein. In one embodiment, a thin barrier layer formed over an organic semiconductor includes a non-conformal organic layer, an inorganic layer formed over the non-conformal organic layer, a metallic layer formed over the inorganic layer and a second organic layer formed over the metallic layer. In another embodiment, a method of depositing a barrier layer includes forming an organic semiconductor device over the exposed surface of a substrate, depositing an inorganic layer using CVD, depositing a metallic layer comprising one or more metal oxide or metal nitride layers over the inorganic layer by ALD, each of the metal oxide or metal nitride layers comprising a metal, wherein the metal is selected from the group consisting of aluminum, hafnium, titanium, zirconium, silicon or combinations thereof and depositing an organic layer over the metallic layer.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 18, 2014
    Inventors: Bhaskar KUMAR, Dieter HAAS
  • Patent number: 8741932
    Abstract: The present invention relates to compounds of formula (I), wherein Ra, Rb, Rc, Rd, Re and Rf are as defined in the specification, processes for their preparation, pharmaceutical compositions containing them and their use in the treatment of diseases mediated by phosphatidylinositol-3-kinase (PI3K), mammalian target of rapamycin (mTOR), Signal transducer and activator of transcription 3 (STAT 3), tumor necrosis factor-? (TNF-?), interleukin-6 (IL-6) or a combination thereof particularly in the treatment of cancer and inflammation.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: June 3, 2014
    Assignee: Piramal Enterprises Limited
    Inventors: Sanjay Kumar, Sivaramakrishnan Hariharan, Mandar Bhonde, Nilesh Dagia, Rajiv Sharma, Pallavi Hanmantrao Mane, Pramod Bhaskar Kumar
  • Publication number: 20120232072
    Abstract: The present invention relates to compounds of formula (I), wherein Ra, Rb, Rc, Rd, Re and Rf are as defined in the specification, processes for their preparation, pharmaceutical compositions containing them and their use in the treatment of diseases mediated by phosphatidylinositol-3-kinase (PI3K), mammalian target of rapamycin (mTOR), Signal transducer and activator of transcription 3 (STAT 3), tumor necrosis factor-? (TNF-?), interleukin-6 (IL-6) or a combination thereof particularly in the treatment of cancer and inflammation.
    Type: Application
    Filed: November 4, 2010
    Publication date: September 13, 2012
    Applicant: PIRAMAL LIFE SCIENCES LIMITED
    Inventors: Sanjay Kumar, Sivaramakrishnan Hariharan, Mandar Bhonde, Nilesh Dagia, Rajiv Sharma, Pallavi Hanmantrao Mane, Pramod Bhaskar Kumar
  • Publication number: 20120080092
    Abstract: Embodiments of the invention provide a method of forming a doped gallium arsenide based (GaAs) layer from a solution based precursor. The doped gallium arsenide based (GaAs) layer formed from the solution based precursor may assist solar cell devices to improve light absorption and conversion efficiency. In one embodiment, a method of forming a solar cell device includes forming a first layer with a first type of dopants doped therein over a surface of a substrate, forming a GaAs based layer on the first layer, and forming a second layer with a second type of dopants doped therein on the GaAs based layer.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 5, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Kaushal K. Singh, Robert Jan Visser, Srikant Rao, Bhaskar Kumar, Claire J. Carmalt, Ranga Rao Arnepalli, Omkaram Nalamasu, Gaurav Saraf, Sanjayan Sathasivam, Christopher Stuart Blackman