Abstract: A circuit includes a phase detector configured to produce a first up signal and a first down signal based on a difference between a reference clock and a feedback clock and a harmonic detector coupled to the phase detector, the harmonic detector configured to produce a second up signal based on the first up signal and whether the harmonic detector detects a harmonic lock between the reference clock and the feedback clock based on a first clock phase and a second clock phase. Additionally, the circuit includes a false lock detector coupled to the phase detector and to the harmonic detector, the false lock detector configured to produce a second down signal based on the first down signal and whether the false lock detector detects a false lock between the reference clock and the feedback clock based on a third clock phase and a fourth clock phase.

Abstract: An example apparatus includes: digitally locked loop (DLL) circuitry coupled to a clock terminal and configured to generate a plurality of delayed clocks at a plurality of delayed clock terminals based on a reference clock of the clock terminal; first retimer circuitry coupled to the plurality of delayed clock terminals, a first data terminal, and a second data terminal, the first retimer circuitry configured to delay and serialize data of the first data terminal and the second data terminal using at least one of the delayed clocks of the plurality of delayed clock terminals; and second retimer circuitry coupled to the plurality of delayed clock terminals, a third data terminal, and a fourth data terminal, the second retimer circuitry configured to delay and serialize data of the third data terminal and the fourth data terminal.

Abstract: A loss of lock detector that includes a logic gate, a voltage-to-current converter coupled to the logic gate, a capacitor coupled to the converter, and a comparator coupled to the capacitor. The logic gate is configured to receive a first error signal and a second error signal from a phase detector, perform an AND function of the first and second error signals, and generate a gate output signal. The converter is configured to receive the gate output signal and generate a stream of current pulses representative of the gate output signal. The capacitor is configured to receive the stream of current pulses and generate a DC signal representative of the stream of current pulses. The comparator is configured to compare the DC signal to a reference signal and output a lock signal.

Abstract: A current mirror with depletion mode MOS devices, and an embedded noise filter, operable with low supply voltage to provide a low-noise mirror current. The current mirror includes depletion-mode MOS transistors M1 and M2 configured as a current mirror, including a reference_current leg including M1 that receives an input reference current, and a mirror_current leg including M2, controlled by M1 to mirror the reference current as an output mirror current. An embedded noise filter (such as a low-pass RC filter) is coupled to M1 and M2, and configured to suppress noise in the input reference current from mirroring to the output mirror current. The embedded noise filter can be a low-pass RC coupled between the M1/M2 (low leakage) gates. Use of depletion-mode MOS devices with near-zero VT offers sufficient head-room for cascoding at low supply voltage to improve accuracy.

Abstract: A loss of lock detector that includes a logic gate, a voltage-to-current converter coupled to the logic gate, a capacitor coupled to the converter, and a comparator coupled to the capacitor. The logic gate is configured to receive a first error signal and a second error signal from a phase detector, perform an AND function of the first and second error signals, and generate a gate output signal. The converter is configured to receive the gate output signal and generate a stream of current pulses representative of the gate output signal. The capacitor is configured to receive the stream of current pulses and generate a DC signal representative of the stream of current pulses. The comparator is configured to compare the DC signal to a reference signal and output a lock signal.

Abstract: A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.

Abstract: A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.

Abstract: Conventional retimers generally consume too much power, are too noisy, and are too large. Additionally, phase noise and jitter are generally a function of retiming. As a result, a retimer is provided with a smaller footprint that has reduced power consumption and improved noise characteristics over other conventional retimers.

Abstract: Traditionally, complementary metal oxide semiconductor (CMOS) and bipolar transistors have been separately employed in low voltage differential signal (LVDS) drivers. Here, a hybridized LVDS driver is provided with an input stage that uses CMOS transistors and output stages that use bipolar transistors. As a result of this hybridization, the LVDS driver has superior functional characteristics compared to conventional LVDS drivers as well as being able to function with a supply range between about 1.8V and 3.3V.

Abstract: Traditionally, complementary metal oxide semiconductor (CMOS) and bipolar transistors have been separately employed in low voltage differential signal (LVDS) drivers. Here, a hybridized LVDS driver is provided with an input stage that uses CMOS transistors and output stages that use bipolar transistors. As a result of this hybridization, the LVDS driver has superior functional characteristics compared to conventional LVDS drivers as well as being able to function with a supply range between about 1.8V and 3.3V.

Abstract: A circuit and method for evaluating serializer deserializer (SERDES) performance that is particularly advantageous when the SERDES has a decision feedback equalizer (DFE). In one embodiment, the circuit has a data processing path and an operational feedback loop coupled to said data processing path and containing an equalizer, perhaps a DFE. In that embodiment, the circuit includes an eye scanning circuit coupled to said data processing path but separate from said equalizer and configured to measure at least one dimension of an eye relative to which said equalizer is configured for operation without substantially affecting said operation.

Abstract: An equalizer comprises a sampler, a filter, and a summer. The sampler samples a signal indicative of an input communication signal to determine digital decision output signals having a communication device data rate. The filter receives digital decision output signals from the sampler and generates equalization signals therefrom. The summer couples to the sampler and the filter and combines together the input communication signal with the equalization signals. Further, a plurality of clocks control timing associated with the sampler. These clocks have frequencies that are less than the predetermined data rate of the digital decision output signals.

Abstract: A filter includes a tap multiplication circuit and a tap digital-to-analog (“DAC”) unit coupled to the tap multiplication circuit. Further, a plurality of clocks are provided that control timing associated with the tap multiplication circuit and that permit one tap multiplication to be output while another tap multiplication is being computed for a 1/N rate implementation.

Abstract: A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential input nodes. The termination circuit comprises a common mode node. A common mode control circuit is connected to the common mode node, and exhibits a substantially zero output impedance. In so doing, the common mode control circuit provides a common mode voltage to the common mode node of the termination circuit that exhibits substantially ideal termination of common mode signals and negligible loading on the differential input nodes. In another aspect, selection circuitry is provided that selectively passes single-ended or differential test signals to the differential input nodes during a test mode of operation. The selection circuitry facilitates observation of signals within the receiver circuitry.

Abstract: A method, and associated storage medium containing software and a system, includes extracting a time domain impulse response from parameters that characterize a communication channel, generating a probability distribution function (PDF) of an output voltage based on the impulse response; and computing a relationship between bit error rate and voltage margin based on the final probability distribution function. Generating the PDF of the output voltage may comprise one or more of the following acts: quantizing the impulse response into a plurality of quantized levels, assigning taps to the quantized levels and determining a number of taps assigned to each quantized level, determining allowable voltage levels for each quantized level, and determining a probability of occurrence of each allowable voltage level, determining a PDF for each voltage level; and convolving all of the PDFs for the various voltage levels to obtain the PDF of the output voltage.

Abstract: A phase lock loop to control phase error including a first phase error detector to detect the phase error in a first mode, a first loop filter to filter a first phase error by using a first factor, a second phase error detector to detect a second phase error in a second mode, a second loop filter to filter a second phase error by using a second factor, and a circuit to select either the first phase error or the second phase error in accordance with the first or second mode.

Abstract: A circuit for use in a phase lock loop including a first phase detector to detect a first phase error between input signals, the first phase detector obtaining the first phase error during a first time period, a second phase detector to detect a second phase error between the input signals, the second phase detector obtaining the second phase error during a second time period, the second time period being longer than the first time period, and a compensation circuit to compensate the first phase error with a portion of the second phase error signal.

Abstract: A phase lock loop to control phase error from a first input signal and a second input signal including a phase error detector to detect a phase error signal between the first input signal and the second input signal at a predetermined rate, a down-sampling circuit to down-sample the phase error signal and to output a down-sampled signal at a reduced rate with respect to the predetermined rate, a loop filter to filter the down-sampled signal to obtain a filtered signal, and an up-sampling circuit to up-sample the filtered signal at the predetermined rate.

Abstract: A data detectors have been invented featuring a fixed decision delays. The detector is comprised of a preliminary detector working on a single sample and releasing a few probably decisions and a signal, pace detector making a final selection among these probable decisions. The final decision is made based on a finite number of observation samples. The signal space detector consists of filter bank, slicers, and a Boolean logic (circuit?).

Abstract: A circuit for use in a phase locked loop includes pre-computation blocks for phase error detector and loop filter functions, a selection block (or multiplexer) of these pre-computed results based on detected (or reference signal) signal, and on ambiguity zone detector deriving the pre-computation blocks.