Abstract: A phase lock loop to control phase error including a first phase error detector to detect the phase error in a first mode, a first loop filter to filter a first phase error by using a first factor, a second phase error detector to detect a second phase error in a second mode, a second loop filter to filter a second phase error by using a second factor, and a circuit to select either the first phase error or the second phase error in accordance with the first or second mode.

Abstract: A phase lock loop to control phase error from a first input signal and a second input signal including a phase error detector to detect a phase error signal between the first input signal and the second input signal at a predetermined rate, a down-sampling circuit to down-sample the phase error signal and to output a down-sampled signal at a reduced rate with respect to the predetermined rate, a loop filter to filter the down-sampled signal to obtain a filtered signal, and an up-sampling circuit to up-sample the filtered signal at the predetermined rate.

Abstract: A circuit for use in a phase lock loop including a first phase detector to detect a first phase error between input signals, the first phase detector obtaining the first phase error during a first time period, a second phase detector to detect a second phase error between the input signals, the second phase detector obtaining the second phase error during a second time period, the second time period being longer than the first time period, and a compensation circuit to compensate the first phase error with a portion of the second phase error signal.

Abstract: A circuit (10) and method for dibit detection in a mass data storage device includes concurrently operating magnitude (16), polarity (18), and peak value (20) qualification circuits. The magnitude qualification circuit (16) produces a magnitude qualification output signal when a magnitude of the read back signal exceeds a predetermined magnitude threshold. The polarity qualification circuit produces a polarity qualification output signal when a polarity of the read back signal is of a predetermined polarity. The peak value qualification circuit produces a peak value qualification output signal at a time at which a peak value of the read back signal occurs during a predetermined period. When the magnitude qualification output signal, the polarity qualification output signal, and the peak value qualification output signals simultaneously occur, a dibit detection signal (118) is produced.