Patents by Inventor Bih-Tiao Lin
Bih-Tiao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7685667Abstract: A method and system for cleaning the wafer after CMP is disclosed. A brush module having at least two brushes placed adjacent to each other and having the wafer placed in between. A dummy roller is in contact with an edge of the wafer and follows a rotation of the wafer, wherein when the wafer is rotated, the brushes clean both sides of the wafer, and the dummy roller detects a rotation speed and a rotation direction of the wafer for adjusting the rotation of the wafer.Type: GrantFiled: June 14, 2005Date of Patent: March 30, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bih-tiao Lin, Jin Lung Linh
-
Publication number: 20060277702Abstract: A method and system for cleaning the wafer after CMP is disclosed. A brush module having at least two brushes placed adjacent to each other and having the wafer placed in between. A dummy roller is in contact with an edge of the wafer and follows a rotation of the wafer, wherein when the wafer is rotated, the brushes clean both sides of the wafer, and the dummy roller detects a rotation speed and a rotation direction of the wafer for adjusting the rotation of the wafer.Type: ApplicationFiled: June 14, 2005Publication date: December 14, 2006Inventors: Bih-tiao Lin, Jin Linh
-
Publication number: 20040235297Abstract: A method of removing excess conductive material over a patterned insulating layer by reverse electroplating. A semiconductor wafer is submerged in an electroplating solution, and the semiconductor wafer functions as an anode in the reverse electroplating process. Bulk conductive material from the wafer surface is deposited to a cathode that is also submerged in the electroplating solution. Damascene conductive regions may be formed using the reverse electroplating process without causing damage to the top surface of the first insulating layer or causing dishing or erosion of top surface of the conductive material.Type: ApplicationFiled: May 23, 2003Publication date: November 25, 2004Inventor: Bih-Tiao Lin
-
Patent number: 6821895Abstract: A dynamically adjustable slurry feed arm and method for adjusting the same in a CMP process including carrying out the CMP process for a predetermined period of time on a substrate comprising a polishing layer to remove a portion of a polishing layer; determining the thickness of the polishing layer at a plurality of predetermined measurement areas comprising at least a polishing layer peripheral portion and a polishing layer center portion; determining a desired subsequent dispensing position to equalize the thickness of the polishing layer; and, adjusting the slurry feed arm to the subsequent dispensing position such that the slurry is dispensed over the polishing pad at the subsequent dispensing position comprising one of closer to the polishing pad center portion and closer to the polishing pad peripheral portion.Type: GrantFiled: February 20, 2003Date of Patent: November 23, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Bih-Tiao Lin, Soon-Kang Huang
-
Publication number: 20040166686Abstract: A dynamically adjustable slurry feed arm and method for adjusting the same in a CMP process including carrying out the CMP process for a predetermined period of time on a substrate comprising a polishing layer to remove a portion of a polishing layer; determining the thickness of the polishing layer at a plurality of predetermined measurement areas comprising at least a polishing layer peripheral portion and a polishing layer center portion; determining a desired subsequent dispensing position to equalize the thickness of the polishing layer; and, adjusting the slurry feed arm to the subsequent dispensing position such that the slurry is dispensed over the polishing pad at the subsequent dispensing position comprising one of closer to the polishing pad center portion and closer to the polishing pad peripheral portion.Type: ApplicationFiled: February 20, 2003Publication date: August 26, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bih-Tiao Lin, Soon-Kang Huang
-
Patent number: 6660629Abstract: A method of fabricating a copper damascene. The method is applicable to a substrate, which substrate has a dielectric layer formed thereon. The method comprising forming a damascene opening in the dielectric layer, forming a barrier layer which conforms to a profile of the damascene opening over the substrate, and forming a conformal copper seeding layer on the barrier layer. A copper layer is then formed on the copper seeding layer, wherein the copper seeding layer has a thickness that is sufficient to fill the damascene opening, followed by forming a conformal protective layer on the copper layer. A first CMP step is performed to remove the protective layer, while a portion of the copper layer outside the damascene opening is removed until the protective layer is completely removed, wherein a first polishing rate is faster than a second polishing rate.Type: GrantFiled: February 14, 2002Date of Patent: December 9, 2003Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Bih-Tiao Lin
-
Patent number: 6604849Abstract: A slurry dilution system with an ultrasonic vibrator capable of diluting slurry in-situ to any desired level of concentration is proposed. Raw slurry and the de-ionized water fed into the slurry dilution system is mixed and homogenized by an ultrasonic vibrator and a mixer. The well-mixed slurry solution is then delivered to a chemical-mechanical polishing station. When the chemical-mechanical station requires slurry of a different concentration, the raw slurry can be diluted to the desired level simply by changing the rate of flow of de-ionized water into the dilution system.Type: GrantFiled: May 11, 2001Date of Patent: August 12, 2003Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bih-Tiao Lin, Meng-Feng Tsai, Rong Jye Jang, Kung-Teng Huang
-
Patent number: 6524950Abstract: A method of fabricating copper damascene. In this invention, only crystalline copper metal layer is formed inside the damascene trench and only amorphous copper metal layer is formed outside the damascene trench. During stacking the copper metal layer, copper metal stacks up to form crystalline copper metal with good lattice packing according to the position of the copper seed layer. Conversely, amorphous copper metal is formed in positions where no copper seed layer exists. Since the amorphous copper metal is softer than the crystalline copper metal, lower pressure and the ordinary slurry are used in chemical mechanical polishing to remove amorphous copper metal layer outside the damascene trench, in order to form a flat-surfaced copper damascene structure.Type: GrantFiled: March 24, 2000Date of Patent: February 25, 2003Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Bih-Tiao Lin
-
Publication number: 20020137305Abstract: A fabrication method is offered for shallow trench isolation structures. The insulating layer is deposited in trenches and on a mask layer on a substrate. The thickness of the insulating layer in the trenches is between the depth of the trenches and the depth of the trenches plus the thickness of the mask layer. Then, the thin layer is formed on the insulating layer. The screen layer is formed on the thin layer above the trenches to protect the thin layer when the thin layer and the insulating layer above active areas are removed. Next, the thin layer above the trenches and the mask layer are removed.Type: ApplicationFiled: October 22, 2001Publication date: September 26, 2002Inventors: Bih-Tiao Lin, Chingfu Lin
-
Patent number: 6454917Abstract: An electroplating tool, which includes at least of a deposition cassette which is installed on a negative electrode and copper piece in an electroplating tank, or a copper rod is installed on the positive electrode of the electroplating room. 25 wafers are installed in the electroplating room, and both ends of each of the wafers are respectively fixed in place by a wafer clamp. The wafer clamp is in contact with the negative electrode, and is electrically connected to the wafer. The copper rod or copper piece that connects to the positive electrode can be a big piece that is installed on the outer side of the deposition cassette opening. It can also assume a comb-like arrangement of 25 pieces, respectively interlocked and extending into the gaps between the wafers. Moreover, in order to increase the even distribution during copper deposition, the present invention further adds a sound wave vibration apparatus at the bottom of and on the two sides of the electroplating tank.Type: GrantFiled: October 30, 2000Date of Patent: September 24, 2002Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Bih-Tiao Lin
-
Publication number: 20020098675Abstract: A method of fabricating a copper damascene. The method is applicable to a substrate, which substrate has a dielectric layer formed thereon. The method comprising forming a damascene opening in the dielectric layer, forming a barrier layer which conforms to a profile of the damascene opening over the substrate, and forming a conformal copper seeding layer on the barrier layer. A copper layer is then formed on the copper seeding layer, wherein the copper seeding layer has a thickness that is sufficient to fill the damascene opening, followed by forming a conformal protective layer on the copper layer. A first CMP step is performed to remove the protective layer, while a portion of the copper layer outside the damascene opening is removed until the protective layer is completely removed, wherein a first polishing rate is faster than a second polishing rate.Type: ApplicationFiled: February 14, 2002Publication date: July 25, 2002Inventor: Bih-Tiao Lin
-
Publication number: 20020048214Abstract: A slurry dilution system with an ultrasonic vibrator capable of diluting slurry in-situ to any desired level of concentration is proposed. Raw slurry and the de-ionized water fed into the slurry dilution system is mixed and homogenized by an ultrasonic vibrator and a mixer. The well-mixed slurry solution is then delivered to a chemical-mechanical polishing station. When the chemical-mechanical station requires slurry of a different concentration, the raw slurry can be diluted to the desired level simply by changing the rate of flow of de-ionized water into the dilution system.Type: ApplicationFiled: May 11, 2001Publication date: April 25, 2002Inventors: Bih-Tiao Lin, Meng-Feng Tsai, Rong Jye Jang, Kung-Teng Huang
-
Patent number: 6343977Abstract: An apparatus and method for conditioning the polishing pad of CMP system by employing a multi-zone conditioner, or dresser. The conditioner comprises a plurality of rollers or disks, which can be well tuned to make down-pressure and rolling speed of the rollers or disks to the extent as desirable. The conditioner further comprises driving means for rotating the polishing rollers or disks. It can make a better uniformity of the pad conditioning and improve the profile of the polished wafers. The apparatus and method for conditioning the polishing pad can be especially used to compensate the uniformity of the incoming films, or the pre-CMP films.Type: GrantFiled: March 14, 2000Date of Patent: February 5, 2002Assignee: Worldwide Semiconductor Manufacturing Corp.Inventors: Shuang-Neng Peng, Bih-Tiao Lin
-
Patent number: 6277751Abstract: A method for planarizing a semiconductor wafer. An insulation layer is formed over the wafer. A spin-on-glass layer is coated over the insulation layer. Subsequently, the spin-on-glass layer is baked to smooth out its upper surface. A chemical-mechanical polishing process is carried out to planarize the insulation layer. The method eliminates recess cavities in the more loosely packed device region of the insulation layer after a planarization process.Type: GrantFiled: February 9, 1999Date of Patent: August 21, 2001Assignee: Worldwide Semiconductor Manufacturing Corp.Inventors: Pao-Kang Niu, Chang-Sheng Lee, Bih-Tiao Lin, Sen-Nan Lee
-
Patent number: 6218307Abstract: A method for fabricating a shallow trench isolation structure. A pad oxide layer and a pad silicon nitride layer are formed over a substrate and are patterned to form a trench in the substrate. A high-density plasma (HDP) oxide layer is formed to fill the trench of a certain thickness. A silicon nitride layer is formed over the substrate. The silicon nitride layer and the oxide layer together form a protruding portion. A chemical-mechanical polishing is performed in a range of from at least removing the protruding portion to exposing the silicon nitride layer. The HDP oxide layer is etched until the HDP oxide layer on the pad silicon nitride layer is removed. The pad silicon nitride layer and the silicon nitride layer are removed by etching.Type: GrantFiled: April 5, 1999Date of Patent: April 17, 2001Assignee: Taiwan Semiconductor Mfg. Co., Ltd.Inventor: Bih-Tiao Lin
-
Patent number: 6180489Abstract: A method for forming planarized shallow trench isolation is described. A nitride layer is deposited over the surface of a semiconductor substrate. A plurality of isolation trenches are etched through the nitride layer into the semiconductor substrate wherein there are at least one wide trench and at least one narrow trench. A first oxide layer is deposited over the first nitride layer and within the isolation trenches wherein the first oxide layer fills the isolation trenches. A capping nitride layer is deposited overlying the first oxide layer. A second oxide layer is deposited overlying the capping nitride layer. The second oxide layer is polished away wherein the second oxide layer and the capping nitride layer are left only within the wide trench. The first and second oxide layers are dry etched away with an etch stop on the capping nitride layer within the wide trench and the first nitride layer wherein the second oxide layer is completely removed.Type: GrantFiled: April 12, 1999Date of Patent: January 30, 2001Assignee: Vanguard International Semiconductor CorporationInventors: Fu-Liang Yang, Bih-Tiao Lin, Wei-Ray Lin, Erik S. Jeng
-
Patent number: 6140240Abstract: A method of removing microscratches in planarized dielectric surfaces covering conductor layers in submicron integrated circuit structures includes a semiconductor substrate having at least one dielectric layer formed thereon followed by a chemical mechanical polishing process for planarization. The removal of microscratches includes depositing a PE-CVD polymer layer to fill the microscratches, caused by CMP planarization, and to cover the planarized dielectric surface with a thin layer of the polymer. Deposition is followed by introducing an etching gas into the CVD chamber for an etch back of the just deposited polymer to well below the depth of the microscratches wherein the deposited polymer has the same etch rate as the dielectric layer formed thereunder.Type: GrantFiled: January 7, 1999Date of Patent: October 31, 2000Assignee: Vanguard International Semiconductor CorporationInventors: Fu-Liang Yang, Bih-Tiao Lin, Tzu-Shih Yen, Bi-Ling Chen, Erik S. Jeng
-
Patent number: 6089969Abstract: A transparent powder-proof housing covers the heater block of a PECVD reactor chamber tightly, thereby to prevent from powder pollution while cleaning the interior of the reactor chamber. The transparent powder-proof housing has two outlets, one for connecting to a vacuum cleaner and the other for human operation inside the reactor chamber. The vacuum cleaner vacuums the powder dust out of the transparent powder-proof housing, thereby to largely reduce the powder pollution in a clean room and the chances to jeopardize human health.Type: GrantFiled: April 2, 1998Date of Patent: July 18, 2000Assignee: Vanguard International Semiconductor CorporationInventors: Min-Yuan Chung, Bih-Tiao Lin, Wen-Chang Tseng
-
Patent number: 6071789Abstract: A method for simultaneously forming a storage node and a plurality of interconnection in fabricating a semiconductor device on a substrate.Type: GrantFiled: November 10, 1998Date of Patent: June 6, 2000Assignee: Vanguard International Semiconductor CorporationInventors: Fu-Liang Yang, Erik S. Jeng, Bih-Tiao Lin, I-Ping Lee
-
Patent number: 6054017Abstract: A chemical mechanical polish apparatus (FIG. 3B) for planarizing a semiconductor wafer (31) is disclosed. The apparatus includes a polishing pad (21) and a polishing head (32). The polishing pad includes a surface for polishing the semiconductor wafer. The surface has a hole (20). The polishing head is cooperatively engaged with the polishing pad. The polishing head holds the semiconductor wafer and applies it against the polishing pad. Both the polishing head and the polishing pad are rotatable.Type: GrantFiled: March 10, 1998Date of Patent: April 25, 2000Assignee: Vanguard International Semiconductor CorporationInventors: Fu-Liang Yang, Bih-Tiao Lin