Patents by Inventor Biju Chandran

Biju Chandran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050126819
    Abstract: Methods and associated apparatus of reducing stress in a package are described in which a package is provided comprising an array of interconnects that are connected to a substrate, and then reducing the stress of the interconnects located near a weak area in the package, during flexure of the substrate, by spring loading the weak area of the package.
    Type: Application
    Filed: December 16, 2003
    Publication date: June 16, 2005
    Inventor: Biju Chandran
  • Publication number: 20050116329
    Abstract: A low resistance package-to-die interconnect scheme for reduced die stresses includes a relatively low melting temperature and yield strength solder on the die and a relatively higher melting temperature and electrically conductive material such as copper on the substrate. A soldered joint connects the solder to the electrically conductive material to couple/connect the die and substrate to one another. The soldered joint is formed by heating the die and solder thereon to at least the melting temperature of the solder and thereafter contacting the molten solder with the conductive material on the substrate, which is at a substantially lower temperature for minimizing residual stress from soldering due to coefficient of thermal expansion mismatch between the substrate and die.
    Type: Application
    Filed: December 10, 2004
    Publication date: June 2, 2005
    Inventors: Biju Chandran, Carlos Gonzalez
  • Publication number: 20050070044
    Abstract: A method of packaging a die includes reflowing the solder to electrically connect the die to a substrate at a first temperature, cooling the die and substrate to a second temperature, and placing a heated epoxy in contact with the die and the substrate. The method also includes holding the die and substrate at the second temperature for a time sufficient to allow the epoxy to cure, and cooling the die, substrate and epoxy. The second temperature is less than the first temperature. In addition, the die and substrate are not cooled to a temperature significantly below the second temperature until after the heated epoxy is placed in contact with the die and substrate.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Sandeep Sane, Biju Chandran
  • Publication number: 20050040498
    Abstract: A microelectronic device and methods of fabricating the same comprising a microelectronic die having an active surface, a back surface, and at least one side. The microelectronic die side comprises a beveled sidewall and a channel sidewall. A metallization layer is disposed on the microelectronic die back surface and the beveled sidewall.
    Type: Application
    Filed: September 14, 2004
    Publication date: February 24, 2005
    Inventors: Rajen Dias, Biju Chandran
  • Publication number: 20050012205
    Abstract: A microelectronic device and methods of fabricating the same comprising a microelectronic die having an active surface, a back surface, and at least one side. The microelectronic die side comprises a trench sidewall, a lip and a channel sidewall. A metallization layer is disposed on the microelectronic die back surface and the trench sidewall.
    Type: Application
    Filed: August 10, 2004
    Publication date: January 20, 2005
    Inventors: Rajen Dias, Biju Chandran
  • Patent number: 6812548
    Abstract: A microelectronic device and methods of fabricating the same comprising a microelectronic die having an active surface, a back surface, and at least one side. The microelectronic die side comprises a trench sidewall, a lip and a channel sidewall. A metallization layer is disposed on the microelectronic die back surface and the trench sidewall.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: November 2, 2004
    Assignee: Intel Corporation
    Inventors: Rajen Dias, Biju Chandran
  • Patent number: 6790709
    Abstract: A microelectronic device and methods of fabricating the same comprising a microelectronic die having an active surface, a back surface, and at least one side. The microelectronic die side comprises a beveled sidewall and a channel sidewall. A metallization layer is disposed on the microelectronic die back surface and the beveled sidewall.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: September 14, 2004
    Assignee: Intel Corporation
    Inventors: Rajen Dias, Biju Chandran
  • Patent number: 6752634
    Abstract: An array of contacts for electrically connecting a semiconductor package to a circuit board. The contacts are carried by a tape having an adhesive border. The tape, along with the contacts, are applied easily to either the substrate or the circuit board using the adhesive border. Each contact is made of two S-shaped pieces in perpendicular directions. The contacts are inserted into holes in the tape and held there by friction.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: June 22, 2004
    Assignee: Intel Corporation
    Inventors: Carlos A. Gonzalez, Biju Chandran
  • Patent number: 6672892
    Abstract: A retention module includes a socket to connect to a package. At least one retention arm is coupled to the socket. The at least one retention arm extends perpendicular to the socket. At least one retention clamp is coupled to the at least one retention arm to secure placement of a heat sink against a surface of a package assembly.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: January 6, 2004
    Assignee: Intel Corporation
    Inventors: Biju Chandran, Carlos A. Gonzalez
  • Publication number: 20030234277
    Abstract: A microelectronic assembly including a plurality of conductive columns extending from a bond pad of a microelectronic device and a conductive adhesive on a land pad of a carrier substrate electrically attached to the conductive columns.
    Type: Application
    Filed: June 25, 2002
    Publication date: December 25, 2003
    Inventors: Rajen Dias, Biju Chandran
  • Patent number: 6600652
    Abstract: A retention module includes a socket to connect to a package. At least one retention arm is coupled to the socket. At least one clamping bar is coupled to the at least one retention arm to secure placement of a heat sink against a surface of a package assembly.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: July 29, 2003
    Assignee: Intel Corporation
    Inventors: Biju Chandran, Carlos A. Gonzalez
  • Publication number: 20030116860
    Abstract: A low resistance package-to-die interconnect scheme for reduced die stresses includes a relatively low melting temperature and yield strength solder on the die and a relatively higher melting temperature and electrically conductive material such as copper on the substrate. A soldered joint connects the solder to the electrically conductive material to couple/connect the die and substrate to one another. The soldered joint is formed by heating the die and solder thereon to at least the melting temperature of the solder and thereafter contacting the molten solder with the conductive material on the substrate, which is at a substantially lower temperature for minimizing residual stress from soldering due to coefficient of thermal expansion mismatch between the substrate and die.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 26, 2003
    Inventors: Biju Chandran, Carlos A. Gonzalez
  • Publication number: 20030102526
    Abstract: A microelectronic device and methods of fabricating the same comprising a microelectronic die having an active surface, a back surface, and at least one side. The microelectronic die side comprises a trench sidewall, a lip and a channel sidewall. A metallization layer is disposed on the microelectronic die back surface and the trench sidewall.
    Type: Application
    Filed: November 30, 2001
    Publication date: June 5, 2003
    Inventors: Rajen Dias, Biju Chandran
  • Publication number: 20030104679
    Abstract: A microelectronic device and methods of fabricating the same comprising a microelectronic die having an active surface, a back surface, and at least one side. The microelectronic die side comprises a beveled sidewall and a channel sidewall. A metallization layer is disposed on the microelectronic die back surface and the beveled sidewall.
    Type: Application
    Filed: November 30, 2001
    Publication date: June 5, 2003
    Inventors: Rajen Dias, Biju Chandran
  • Publication number: 20030063440
    Abstract: A retention module includes a socket to connect to a package. At least one retention arm is coupled to the socket. At least one clamping bar is coupled to the at least one retention arm to secure placement of a heat sink against a surface of a package assembly.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventors: Biju Chandran, Carlos A. Gonzalez
  • Publication number: 20030064618
    Abstract: A retention module includes a socket to connect to a package. At least one retention arm is coupled to the socket. The at least one retention arm extends perpendicular to the socket. At least one retention clamp is coupled to the at least one retention arm to secure placement of a heat sink against a surface of a package assembly.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventors: Biju Chandran, Carlos A. Gonzalez
  • Publication number: 20030060061
    Abstract: An array of contacts for electrically connecting a semiconductor package to a circuit board. The contacts are carried by a tape having an adhesive border. The tape, along with the contacts, are applied easily to either the substrate or the circuit board using the adhesive border. Each contact is made of two S-shaped pieces in perpendicular directions. The contacts are inserted into holes in the tape and held there by friction.
    Type: Application
    Filed: September 21, 2001
    Publication date: March 27, 2003
    Inventors: Carlos A. Gonzalez, Biju Chandran
  • Patent number: 6310773
    Abstract: A heat dissipation system for an integrated circuit assembly uses a compressible support structure to support a cooling solution, or heat sink, that dissipates heat generated by an integrated circuit. The compressible support structure, in one embodiment, is a deformable tube that is supported by a base structure. The tube, heat sink and base can be formed from a conductive material to provide an EMI shield for the integrated circuit. Retention mechanisms are used to provide either a fixed or an adjustable compression force to place the heat sink in thermal contact with the integrated circuit. The compressible support structure supports the heat sink, but also absorbs vibration and shock forces exerted on the heat sink to reduce the amount of forces transferred to the integrated circuit.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: October 30, 2001
    Assignee: Intel Corporation
    Inventors: Imran Yusuf, Biju Chandran
  • Patent number: 6256199
    Abstract: An integrated circuit cartridge and method has been described. The cartridge includes a heat pipe that comes in thermal contact with at least one integrated circuit die. A spring clip is utilized to provide a compressive force to maintain a substantially even bond line thickness in the presence of opposing forces, such as forces caused by thermal cycling, power cycling, shocks, and vibration. The spring clip can modulate the compressive force applied as a function of parameters on the spring clip. Parameters include load arm width, load arm thickness, load arm curvature, and the location of tabs relative to load arms. A cartridge cover supplies physical protection for pins that protrude from the cartridge. The cartridge cover also supplies key features that aid in alignment of the pins and a socket.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: July 3, 2001
    Assignee: Intel Corporation
    Inventors: Imran Yusuf, Hong Xie, Johnny M. Cook, Jr., Peter Brandenburger, Biju Chandran, Hamid Ekhlassi