Patents by Inventor Bill Hsu
Bill Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9074940Abstract: The present invention provides a miniature light sensing assembly comprising a light sensing device, a computing device and a connecting member. The light sensing device comprises a main body having an entrance, a light detecting unit disposed in the main body and receiving light travelling through the entrance, a processing module disposed in the main body and converting the light into a photoelectric signal, a connecting unit disposed on the main body, and a signal transmitting module transmitting the photoelectric signal wirelessly. The connecting member is adapted to couple with the light sensing device through the connecting unit. The photoelectric signal is transmitted from the signal transmitting module to the computing device wirelessly and converted into information required by a user by the computing device.Type: GrantFiled: January 28, 2014Date of Patent: July 7, 2015Assignee: AsenseTek Inc.Inventor: Bill Hsu
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Publication number: 20150036139Abstract: The present invention provides a miniature light sensing assembly comprising a light sensing device, a computing device and a connecting member. The light sensing device comprises a main body having an entrance, a light detecting unit disposed in the main body and receiving light travelling through the entrance, a processing module disposed in the main body and converting the light into a photoelectric signal, a connecting unit disposed on the main body, and a signal transmitting module transmitting the photoelectric signal wirelessly. The connecting member is adapted to couple with the light sensing device through the connecting unit. The photoelectric signal is transmitted from the signal transmitting module to the computing device wirelessly and converted into information required by a user by the computing device.Type: ApplicationFiled: January 28, 2014Publication date: February 5, 2015Applicant: Asense Tek Inc.Inventor: Bill Hsu
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Publication number: 20040163199Abstract: A steam cleaner includes a water pump to supply water from a water tank to a heater, and the heater heats it up to become steam to be shot out of a base so as to be used for washing a floor. The steam cleaner also has a water volume button for controlling operating frequency of the water pump to change steam volume to be shot out, by handling of a switch button fixed on a handle to control start and close of washing and operating condition. The grip of the handle is pivotally connected to the base with no limited stages so that the handle can be inclined to one of numerous angles to suit to the height of a user for conveniently using the steam cleaner. And a support base is provided for the steam cleaner to rest thereon for storing away when not used.Type: ApplicationFiled: February 20, 2003Publication date: August 26, 2004Inventor: Bill Hsu
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Publication number: 20040148810Abstract: An ice and snow remover includes a covering part, an electric heat generating part disposed in the covering part for melting ice and snow, two temperature sensors, and a display fitted to the covering part. The temperature sensors are connected to the heat generating part, and disposed in the covering part respectively, and are electrically connected to the display so that temperature of the heat generating part and temperature inside the covering part can be sensed and displayed, helping a user use the ice and snow remover and preventing the user from getting burnt due to touching the remover to try to find out the temperature of the remover when the remover is very hot.Type: ApplicationFiled: February 5, 2003Publication date: August 5, 2004Inventor: Bill Hsu
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Publication number: 20020016063Abstract: A method of fabricating a metal plug comprises steps of providing a substrate and forming a dielectric layer on the substrate with an opening to expose part of the substrate. The method further comprises steps of forming a metal layer on the dielectric layer, forming a first barrier layer by chemical vapor deposition (CVD) to provide a better step coverage, and forming a second barrier layer by physical vapor deposition (PVD) to make the barrier layer harder and less water absorptive. A metal layer is then formed on the second barrier layer and is removed by etching back to form the metal plug.Type: ApplicationFiled: May 27, 1999Publication date: February 7, 2002Inventors: MING-SHING CHEN, BILL HSU
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Publication number: 20010018265Abstract: A method of manufacturing an interconnect. A wafer having an edge region and an interior region is provided. An insulating layer is formed on the wafer. An opening penetrating through the insulating layer in the interior region is formed and a portion of the insulating layer is removed to expose the surface of the wafer in the edge region, simultaneously. A conductive layer is formed on the insulating layer and the wafer exposed by the insulating layer and fills the opening. The conductive layer is patterned to form a wire in the opening.Type: ApplicationFiled: February 20, 2001Publication date: August 30, 2001Inventors: Chien-Chih Lin, Bill Hsu, Nien-Tsu Peng
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Patent number: 6214722Abstract: A method of manufacturing an interconnect on a wafer having an edge region and an interior region comprises the steps of: forming an insulating layer on the wafer having an interior region and an edge region; forming an opening penetrating through the insulating layer in the interior region and removing a portion of the insulating layer to expose a surface of the wafer in the edge region, simultaneously; forming a conductive layer over the insulating layer and the exposed surface of the wafer and filling the opening; and patterning the conductive layer to form a wire in the opening.Type: GrantFiled: April 5, 1999Date of Patent: April 10, 2001Assignee: United Microelectronics Corp.Inventors: Chien-Chih Lin, Bill Hsu, Nien-Tsu Peng
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Patent number: 5994225Abstract: A method for etching metal which can increase the metal-to-photoresist etching selectivity of a metal layer aimed to be etched with respect to a photoresist layer overlaying the metal layer. The method includes a first step of forming a cap oxide layer over the metal layer; a second step of forming a photoresist layer with a desired pattern over the cap oxide layer; a third step of conducting an ion implantation process on the photoresist layer; and a final step of conducting an etching process on the semiconductor wafer by using the photoresist layer as a mask so as to etch away exposed portions of the metal layer that are uncovered by the photoresist layer. Through experiments, it is found that the invention provides a significantly improved etching selectivity over the prior art.Type: GrantFiled: October 18, 1996Date of Patent: November 30, 1999Assignee: United Microelectronics Corp.Inventors: Ming-Tsung Liu, Tsung-Yuan Hung, Bill Hsu
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Patent number: 5514623Abstract: A multi-level conductive interconnection for an integrated circuit is formed in a silicon substrate, wherein there are large contact pad areas at the periphery of the interconnection. A patterned layer of a polysilicon layer is formed on the substrate to act as a first contact to the integrated circuit. An insulating layer is formed over the polysilicon layer, and openings to the polysilicon layer are formed through the insulating layer. A first layer of metal is formed on the insulator such that the metal electrically connects to the polysilicon through the openings, and also forms large contact pad areas. The first metal is patterned to form an electrical break between the large contact pad areas and the integrated circuit. This break prevents electrical damage to the integrated circuit due to charge build-up during subsequent processing in a plasma environment. A second insulating layer is formed and patterned to provide openings for vias to the first metal layer.Type: GrantFiled: February 13, 1995Date of Patent: May 7, 1996Assignee: United Microelectronics CorporationInventors: Joe Ko, Bill Hsu
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Patent number: 5393701Abstract: A multi-level conductive interconnection for an integrated circuit is formed in a silicon substrate, wherein there are large contact pad areas at the periphery of the interconnection. A patterned layer of a conductive polysilicon is formed on the substrate to act as a first conductive contact to the integrated circuit. An insulating layer is formed over the polysilicon layer, and openings to the polysilicon layer are formed through the insulating layer. A first layer of metal is formed on the insulator such that the metal electrically connects to the polysilicon through the openings, and also forming large contact pad areas. The first metal is patterned to form an electrical break between the large contact pad areas and the integrated circuit. This break prevents electrical damage to the integrated circuit due to charge build-up during subsequent processing in a plasma environment. A second insulating layer is formed and patterned to provide openings for vias to the first metal layer.Type: GrantFiled: April 8, 1993Date of Patent: February 28, 1995Assignee: United Microelectronics CorporationInventors: Joe Ko, Bill Hsu
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Patent number: D479376Type: GrantFiled: February 5, 2003Date of Patent: September 2, 2003Inventor: Bill Hsu