Abstract: Disclosed herein is a double-headed swash type compressor, and a distance between an outer peripheral surface of a shaft (20) and an inner peripheral surface of a shaft bore (11) is greater than a distance between the outer peripheral surface of the shaft (20) and an inner peripheral surface of a journal bearing (30).

Abstract: Disclosed herein is a double-headed swash type compressor, and a distance between an outer peripheral surface of a shaft (20) and an inner peripheral surface of a shaft bore (11) is greater than a distance between the outer peripheral surface of the shaft (20) and an inner peripheral surface of a journal bearing (30).

Abstract: A non-volatile multi-level cell (“MLC”) memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory cells, with each non-volatile memory cell storing multiple groups of bits. A row buffer in the memory device has multiple buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write latencies and energies.

Abstract: A multi-level cell memory includes a memory cell that stores two or more bits of information; a sensing circuit coupled to the memory cell; and a row buffer structure comprising a split page buffer having a first page buffer and a second page buffer. The sensing circuit operates to read from the memory cell, places a first bit in one of the first page buffer and the second page buffer, and places the second bit in one of the first page buffer and the second page buffer.

Abstract: An image forming apparatus and a method of controlling power-saving modes of the image forming apparatus are provided. The method of controlling power-saving modes of the image forming apparatus includes beginning a first power-saving mode after standing by in a normal mode for first time if no print operation is implemented, and beginning a second power-saving mode after standing by in the normal mode for second standby time if an error occurs under implementation of a print operation, wherein the second time is shorter than the first time, and the second power-saving mode includes a an error-checking mode.

Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device; and a controller configured to receive a write command from a host and program write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device.

Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state; and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result.

Abstract: A non-volatile multi-level cell (“MLC”) memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory cells, with each non-volatile memory cell storing multiple groups of bits. A row buffer in the memory device has multiple buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write latencies and energies.

Abstract: Disclosed are a phenyl-isoxazol derivative compound, which is useful as a treatment material for virus infection, especially, infection of an influenza virus, or its pharmaceutically acceptable derivative, a preparation method thereof, and an illness treatment pharmaceutical composition including the compound as an active ingredient.

Abstract: A multi-level cell memory includes a memory cell that stores two or more bits of information; a sensing circuit coupled to the memory cell; and a row buffer structure comprising a split page buffer having a first page buffer and a second page buffer. The sensing circuit operates to read from and write to the memory device, places a first bit in one of the first page buffer and the second page buffer, and places the second bit in one of the first page buffer and the second page buffer.

Abstract: A method and apparatus to interface a semiconductor storage device and a host in order to provide performance throttling of the semiconductor storage device. In the method, the semiconductor storage can receive a setting request command from the host. The semiconductor storage device sets a performance throttling parameter to a particular value in response to the setting request command. The semiconductor storage device can send to the host a setting response signal indicating completion of the setting of the performance throttling parameter.

Abstract: An image forming apparatus includes a power supply unit to generate DC power, a plurality of function units to perform the functions of the image forming apparatus, a control unit to control the operation of a plurality of function units, a switching unit to receive DC power of the power supply unit and switch power provided to the control unit and each of a plurality of function units, and a power management unit to receive DC power of the power supply unit and to control a switching operation of the switching unit according to an operation mode of the image forming apparatus.

Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state; and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result.

Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device; and a controller configured to receive a write command from a host and program write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device.

Abstract: An image forming apparatus and a method of controlling power-saving modes of the image forming apparatus are provided. The method of controlling power-saving modes of the image forming apparatus includes beginning a first power-saving mode after standing by in a normal mode for first time if no print operation is implemented, and beginning a second power-saving mode after standing by in the normal mode for second standby time if an error occurs under implementation of a print operation, wherein the second time is shorter than the first time, and the second power-saving mode includes a an error-checking mode.

Abstract: A semiconductor storage device (SSD) and a method of throttling performance of the SSD are provided. The method can include includes gathering at least two workload data items related with to a workload of the semiconductor storage device, estimating the workload using the at least two workload data items, and throttling the performance of the semiconductor storage device according to the estimated workload. Accordingly, a workload that the semiconductor storage device will undergo can be estimated.

Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state, and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result.

Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device, and a controller configured to receive a write command from a host and program and to write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device.