Abstract: Provided are high power PLC optical Tx module and PLC optical Tx/Rx module. The PLC optical Tx/Rx module is located in an OLT of a PON system. The high power PLC optical Tx/Rx module includes a photodiode, a laser diode, an SOA, an optical coupler, and a PLC platform. The photodiode converts an input optical signal into an electrical signal, and the laser diode generates an optical signal of a predetermined wavelength. The SOA amplifies the optical signal generated by the laser diode, and the optical coupler couples optical signals, outputs the coupled signal to a splitter, divides an optical signal from the slitter, and outputs the divided signals to the photodiode. The PLC platform incorporates the photodiode, the laser diode, the SOA, and the optical coupler into one package to allow an optical signal to be output with high power.

Abstract: A pluggable optical transceiver module is provided. The pluggable optical transceiver module is fitted to and removed from a receptacle having a clamp at an end in an optical communication system body and includes a housing frame having an adaptor at which a light emitting diode (LED) display unit and an optical transceiver element are installed; a rotary lever comprising a handle at one side and a pressing portion at another side so that the rotary lever rotates by a predetermined angle with respect to one side of the housing frame; and an elastic arm which is pivoted on the housing frame to be rotated by the rotary lever and includes one end contacting the pressing portion according to rotation of the rotary lever and another end coupled with or separated from the clamp of the receptacle by the rotation.

Abstract: An apparatus and method for reducing a pattern jitter is provided that uses a local symmetry forcing wave signal. Pattern jitter is generated when a timing phase of a symbol signal is recovered. The apparatus can include a demultiplexer receiving a preamble and data signal. A nonlinear operation unit preferably only receives the preamble signal from the demultiplexer, and a locally symmetric wave generator preferably only receives the data signal from the demultiplexer. A buffer memory selects from an output signal of the nonlinear operation unit and an output signal of the locally symmetric wave generator. An input signal controller receives a control signal and outputs an input control signal to control the buffer memory and the demultiplexer. The apparatus and method that reduces pattern jitter is a system with reduced complexity and reduced cost to advantageously embody a very large scale integration VLSI or the like.

Abstract: A data transmission apparatus and method in a pulse amplitude modulation (PAM) communication system that converts information to be transmitted into digital data, converts the digital signal into an analog signal, modulates the analog signal using a PAM modulator, and transmits the signal through a predetermined transmission channel. The method includes detecting distortion in the signal to be transmitted to the transmission channel; generating compensation information corresponding to the distortion detected; and changing digital data to be input to the PAM modulator based upon the compensation information generated.

Abstract: A phase locked loop (PLL) using a gear shifting algorithm, includes a phase detector comparing phases of an external clock signal and a feedback internal clock signal, a gear shifting control unit outputting a plurality of control signals according to a programmed variable loop gain sequence and an output signal from the phase detector, a charge pump controlling a loop gain of a pumping voltage according to the plurality of control signals, a loop filter filtering an output signal from the charge pump, and a voltage controlled oscillator controlling a frequency of the second clock signal according to an output signal from the loop filter.

Abstract: A timing restoration circuit for a pulse amplitude modulation (PAM)-type communication system which is capable of effectively preventing interference between a plurality of receiving devices caused by phase locked loops (PLL) being disposed in one chip when a plurality of channels are employed. The PAM type communication system includes a logical operator and comparator for logically operating and comparing signals sequentially delayed in a single PLL with the received signal of each channel. The system then generates a selective control signal for selecting a signal from among the sequentially delayed signals closest to a timing of the received signal, and multiplexers are utilized for selecting the signals from among the output signals from the PLL closest to the timing of the received signals on the basis of the selective control signals outputted from the logical operator and comparator and outputting the selected signal as sampling pulse signals of each channel.