Abstract: A voltage-to-current conversion circuit includes an error amplifier (12A) which amplifies a voltage difference between the drains of the first (6) and second (7) transistors of a first current mirror, wherein drain current of the first transistor is proportional to an input voltage (Vin). The output of the error amplifier is connected to the gates of the first and second transistors. A compensation capacitor is coupled between the gate and drain of the first transistor. The drain current of the second transistor flows through a cascode transistor (16) to an input of a second current mirror, an output transistor (31) of which provides a current (Ibias) which is proportional to the input voltage (Vin) as a bias current for the error amplifier, to provide stable operation.

Abstract: A phase detector in a delay locked loop circuit operates to determine the status of propagation of a first pulse of a reference clock signal (CKref) through a delay line (21). A first control signal (DOWN) is produced a in response to represent a first time at which the first pulse has progressed entirely through the delay line (21) and a later second time at which a next second pulse of the reference clock signal (CKref) arrives at a first input of the phase detector (24A). The delay of the delay line (21) is reduced in response to the first control signal (DOWN). A second control signal (UP) is produced in response to the status to represent a third time at which the second pulse of the reference clock signal (CKref) arrives at the first input of the phase detector (24A) and a later fourth time at which the first pulse of the reference clock signal (CKref) has progressed to the end of the delay line (21) and is used to increase the delay of the delay line (21).

Abstract: A phase detector in a delay locked loop circuit operates to determine the status of propagation of a first pulse of a reference clock signal (CKref) through a delay line (21). A first control signal (DOWN) is produced a in response to represent a first time at which the first pulse has progressed entirely through the delay line (21) and a later second time at which a next second pulse of the reference clock signal (CKref) arrives at a first input of the phase detector (24A). The delay of the delay line (21) is reduced in response to the first control signal (DOWN). A second control signal (UP) is produced in response to the status to represent a third time at which the second pulse of the reference clock signal (CKref) arrives at the first input of the phase detector (24A) and a later fourth time at which the first pulse of the reference clock signal (CKref) has progressed to the end of the delay line (21) and is used to increase the delay of the delay line (21).

Abstract: A voltage-to-current conversion circuit includes an error amplifier (12A) which amplifies a voltage difference between the drains of the first (6) and second (7) transistors of a first current mirror, wherein drain current of the first transistor is proportional to an input voltage (Vin). The output of the error amplifier is connected to the gates of the first and second transistors. A compensation capacitor is coupled between the gate and drain of the first transistor. The drain current of the second transistor flows through a cascode transistor (16) to an input of a second current mirror, an output transistor (31) of which provides a current (Ibias) which is proportional to the input voltage (Vin) as a bias current for the error amplifier, to provide stable operation.

Abstract: A mixed signal system includes a digital circuit (17) clocked by a digital clock signal, an analog circuit (18) clocked by an analog clock signal, and clock generation circuitry (15) including a delay locked loop (20) including a N-cell delay line (21) having an input for receiving a reference clock signal and a plurality of delay outputs (22), and a multiplexer (30) having a plurality of inputs coupled to the plurality of delay outputs (22), respectively. A selection signal (34) causes the multiplexer (30) to couple a selected one of the delay outputs (22) to an output (32) of the multiplexer (30) so as to cause the analog clock signal and the digital clock signal to be sufficiently skewed from each other to minimize an inaccuracy in the analog circuit (18) caused by a noise glitch associated with the digital clock signal.

Abstract: Bias current in output transistors of a class AB output stage is controlled by providing equal amplification to both an output of an input stage (2) of an amplifier and an output (17,18) of a class AB control circuit (46). A split input transistor circuit structure for a first side of the differential input stage (2) includes first (15) and second (16) input transistors with gates coupled to a first input (Vin+). A third input transistor (10) of the input stage has a gate coupled to a second input (Vin−). A split folded common gate cascode circuit includes first (25) and second (30) cascode transistors having their drains coupled to gates of the output transistors, respectively, and a third cascode transistor has a source coupled to a drain of the third input transistor.

Abstract: A voltage monitor circuit for biasing a well region of a CMOS circuit includes a self-biased comparator which compares first (INP) and second (INN) input signals. The comparator includes first (MN1) and second (MN2) N-channel transistors with grounded sources, a drain of the first N-channel transistor and a gate of the second N-channel transistor being coupled to a first output (OUTN), and a drain of the second N-channel transistor and a gate of the first N-channel transistor being coupled to a second output (OUTP). First (MP1) and second (MP2) P-channel transistors are operated to couple the second or first input signal to the second or first output, respectively, by controlling the gate-to-source voltage of the first or second P-channel transistor according to the polarity of a voltage difference between the first and second input signals.

Abstract: Bias current in output transistors of a class AB output stage is controlled by providing equal amplification to both an output of an input stage (2) of an amplifier and an output (17,18) of a class AB control circuit (46). A split input transistor circuit structure for a first side of the differential input stage (2) includes first (15) and second (16) input transistors with gates coupled to a first input (Vin+). A third input transistor (10) of the input stage has a gate coupled to a second input (Vin−). A split folded common gate cascode circuit includes first (25) and second (30) cascode transistors having their drains coupled to gates of the output transistors, respectively, and a third cascode transistor has a source coupled to a drain of the third input transistor.

Abstract: A Miller de-compensation technique and circuit is provided for a differential input, differential output (DIDO) amplifier that facilitates increased differential mode bandwidth while maintaining common-mode and differential mode stability. An exemplary differential input, differential output (DIDO) amplifier comprises a pair of op amps having a compensation capacitance circuit. The compensation capacitance circuit is configured to distinguish between differential mode signals and common mode signals, and to reduce the effects of compensation capacitance during differential mode operation, but allow the effects of compensation capacitance to remain present during common mode operation. As a result, the amount of compensation capacitance can be configured such that common mode stability can be maintained without reducing differential mode bandwidth. The DIDO amplifier can be configured as a programmable gain amplifier or a fixed gain amplifier.

Abstract: A Miller de-compensation technique and circuit is provided for a differential input, differential output (DIDO) amplifier that facilitates increased differential mode bandwidth while maintaining common-mode and differential mode stability. An exemplary differential input, differential output (DIDO) amplifier comprises a pair of op amps having a compensation capacitance circuit. The compensation capacitance circuit is configured to distinguish between differential mode signals and common mode signals, and to reduce the effects of compensation capacitance during differential mode operation, but allow the effects of compensation capacitance to remain present during common mode operation. As a result, the amount of compensation capacitance can be configured such that common mode stability can be maintained without reducing differential mode bandwidth. The DIDO amplifier can be configured as a programmable gain amplifier or a fixed gain amplifier.

Abstract: An input buffer circuit for use with an analog-to-digital converter is provided. The input buffer circuit comprises a first amplifier configured with a second amplifier to improve the overall gain of the input buffer circuit. The first amplifier comprises a differential pair of transistors configured with a second pair of transistors comprising a current mirror arrangement, wherein one of the differential pair of transistors of the first amplifier is configured in a diode-connected arrangement to provide a first feedback loop, while the second amplifier comprises a differential pair of transistors configured with another pair of transistors also comprising a current mirror arrangement, with the second amplifier and the current mirror arrangement of the first amplifier comprising a second feedback loop.

Abstract: A method and apparatus for performing gain calibration of an analog to digital converter is provided. During a calibration mode, an input sampling circuit comprised of multiple branches can be configured to provide a calibration mode gain of one. The analog-to-digital converter selects one of the parallel capacitor input sampling branches and repetitively samples the whole charge associated with the calibration voltage signal. This sampling step is repeated for each input sampling branch that is used during normal operation mode. The results of the sampling of the branches may be suitably averaged to create a gain calibration coefficient that is representative of and accounts for sampling variations between the input branches.

Abstract: An input buffer circuit for use with an analog-to-digital converter is provided. The input buffer circuit is configured to increase the input impedance of the switched-sampling circuit of the analog-to-digital converter, and thus reduce the loading of the input voltage terminal. The input buffer circuit can comprise a first amplifier configured with a second amplifier to improve the overall gain of the input buffer circuit. The first amplifier comprises a differential pair of transistors configured with a second pair of transistors comprising a current mirror arrangement, wherein one of the differential pair of transistors of the first amplifier is configured in a diode-connected arrangement to provide a first feedback loop, while the second amplifier comprises a differential pair of transistors configured with another pair of transistors also comprising a current mirror arrangement, with the second amplifier and the current mirror arrangement of the first amplifier comprising a second feedback loop.

Abstract: A method and apparatus for performing gain calibration of an analog to digital converter is provided. During a calibration mode, an input sampling circuit comprised of multiple branches can be configured to provide a calibration mode gain of one. The analog-to-digital converter selects one of the parallel capacitor input sampling branches and repetitively samples the whole charge associated with the calibration voltage signal. This sampling step is repeated for each input sampling branch that is used during normal operation mode. The results of the sampling of the branches may be suitably averaged to create a gain calibration coefficient that is representative of and accounts for sampling variations between the input branches.

Abstract: An analog-to-digital converter includes a delta sigma modulator (103) adapted to produce a stream of pulses (104) the density of which represents the amplitude of an analog input signal (VIN) coupled to an input of the delta sigma modulator. A decimation filter (105) is coupled to filter the stream of pulses and produce a digital word (106) representing the amplitude of the analog input signal. A serial interface circuit (109) is coupled to serially receive the bits of the output word and serially shift the bits of the digital word to a data terminal (110). A timing generator (17) produces timing signals to control operation of the delta sigma modulator and the decimation filter and generates a conversion done signal (21) indicative of completion of conversion of the analog input signal (VIN) into the digital word.

Abstract: An FIR decimation filter includes the a shift register (51) including M flip-flops arranged in M/R rows (52, 54, 56, 58) of R bits each, wherein M/R is an integer and R is the decimation ratio of the FIR decimation filter. The shift register has an input for receiving serial digital input information. Half of the rows are sequentially arranged in an upper section and the other half of the rows are arranged sequentially in a lower section. Each row has a left tap and a right tap. The shift register includes a bidirectional shift register in the top row of the lower section. A control circuit (70) controls shifting operations which each shift input data and data present in the shift register (51) by R bits so as to load a new group of R bits into each row.

Abstract: An FIR decimation filter includes the a shift register (51) including M flip-flops arranged in M/R rows (52, 54, 56, 58) of R bits each, wherein M/R is an integer and R is the decimation ratio of the FIR decimation filter. The shift register has an input for receiving serial digital input information. Half of the rows are sequentially arranged in an upper section and the other half of the rows are arranged sequentially in a lower section. Each row has a left tap and a right tap. The shift register includes a bidirectional shift register in the top row of the lower section. A control circuit (70) controls shifting operations which each shift input data and data present in the shift register (51) by R bits so as to load a new group of R bits into each row.

Abstract: A method and apparatus for recovering from an unstable oscillating condition in a delta-sigma A/D converter modulator circuit. A modulator circuit is disclosed having integrator stages, each having a first switch across the input terminals of the integrator stage and a second switch across the output terminals of the integrator stage. In another embodiment of the invention, the integrator stage comprises a differentially structured operational amplifier having a first restore switch coupled across the input terminals, a second restore switch across the output terminals, and four disconnect switches, one each coupled between the operational amplifier inputs and ends of the first restore switch and between the operational amplifier outputs and ends of the second restore switch. In operation, an unstable condition detector monitors an output of the A/D modulator circuit and generates a restore signal to the integrator stages upon detection of an unstable condition.

Abstract: A delta sigma modulator system includes a delta sigma modulator (9) including a summing circuit (3) having a first input connected to receive an input signal (2), loop filter circuitry (5) having an input coupled to an output of the summing circuit (3), and comparator circuitry (22) having an input coupled to an output of the loop filter circuitry (5) and also having an output coupled to an output (23) of the delta sigma modulator (9). The density of the dither is adjusted in accordance with changes in the magnitude of the input signal. This is accomplished by performing a coarse digital filtering of an output signal (23) produced by the delta-sigma modulator (9), wherein noise present in the output signal (23) produced by the delta sigma modulator (9) causes a probability distribution of the occurrence of pulses constituting a filtered output signal (25) produced by the coarse filtering. A dither disable signal is produced if the filtered output signal (25) is not within a first threshold window.

Abstract: A system for reducing sensitivity of an integrated circuit chopper-stabilized amplifier to intermodulation applies a pseudo-random sequence signal (11A) to an LSB of a first input of a first adder. An error feedback signal (18) is applied to a second input of the first adder and a first input of a second adder (16). A 1-bit quantization signal (&phgr;CH) is produced as an MSB of an output of the first adder and applied to an LSB of a second input of the second adder (16). An error signal (16A) representing the difference between the quantization signal (&phgr;CH) and the error feedback signal (18) is produced by the second adder (16). The error signal (16A) is delayed a predetermined amount to produce the error feedback signal (18), wherein energy of the quantization signal (&phgr;CH) is spread over a broad frequency spectrum between DC and FS/2. A pair of out-of-phase, non-overlapping chopping signals from the quantization signal (&phgr;CH).