Abstract: A power supply circuit includes a first power supply circuit and a second power supply circuit. The first power supply circuit includes a first battery and a DC/DC converter, an input end of the DC/DC converter is connected to the first battery, and an output end of the DC/DC converter is configured to supply power to a battery management system (BMS) of the first battery, a controller of the DC/DC converter, and one or more first loads.

Abstract: Described herein are compounds that inhibits the membrane proximal external region (MPER) of a viral envelope (Env), as well as and compositions thereof. Further provided herein are methods for treating or preventing a viral infection comprises administering to a subject in need thereof an agent or compound that inhibits the MPER of a viral Env. In certain embodiments, the viral infection is an HIV infection.

Abstract: Provided herein, in some aspects, are methods for using the receptor-binidng domain (RBD) of the SARS-COV-2 S protein, including the the RBD-1, RBD-2, and/or RBD-3 regions, to identify therapeutics for the treatment of SARS-COV-2, developing a vaccine for the treatment or prevention of SARS-COV-2, and identifying a patient as being in need for a treatment for SARS-COV-2.

Abstract: A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

Abstract: A static random-access memory (SRAM) circuit and associated read operation method and write operation method are provided. The SRAM circuit includes memory units arranged in M columns and N rows, M bit lines, N row-voltage selection lines, N word lines, and a control circuit. The control circuit includes a controller, a voltage source, a voltage selection module, a word-line driving module, and a bit-line driving module. The voltage source provides a first voltage and a second voltage. When the control circuit performs access to the memory unit located in the mth column and the nth row, the voltage selection module transmits one of the first voltage and the second voltage to an nth row-voltage selection line. The voltage selection module transmits the second voltage to the other (N?1) row-voltage selection lines. The variables M, N, m, and n are positive integers.

Abstract: A power transmission and transformation project acceptance method based on building information modeling (BIM) and point cloud measurement includes: S1: constructing a BIM model based on a design drawing, where the BIM model includes standard parameters of key components of a power transmission and transformation project; S2: obtaining point cloud data, and constructing a point cloud data model based on the point cloud data, where the point cloud data model includes actual parameters of the key components of the power transmission and transformation project; S3: comparing the BIM model with the point cloud data model to obtain construction acceptance data; and S4: visualizing the construction acceptance data and outputting an acceptance report to complete acceptance of the power transmission and transformation project. The BIM model and the point cloud data model are compared to implement rapid and efficient acceptance of the power transmission and transformation project.

Abstract: An error detection and correction method is provided. The method includes: when a pipeline stage error is detected, correcting the pipeline stage error; when it is determined that a plurality of cascaded pipeline stage circuits have continuous pipeline stage errors, stopping all operations of all pipeline stage circuits; flushing the data of the pipeline stage circuits; and re-processing the data of the pipeline stage circuits at a downclocked frequency.

Abstract: Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.

Abstract: An error detection and correction method is provided. The method includes: when a pipeline stage error is detected, correcting the pipeline stage error; when it is determined that a plurality of cascaded pipeline stage circuits have continuous pipeline stage errors, stopping all operations of all pipeline stage circuits; flushing the data of the pipeline stage circuits; and re-processing the data of the pipeline stage circuits at a downclocked frequency.

Abstract: A method for processing previously detected identifications of apparatuses of an aircraft, wherein each apparatus has at least one communicative component. A reference dataset is used to compare the actual identifications with specified identifications, as a result of which a report signal based on the comparison result indicates whether the detected identifications correspond to the identifications represented by the reference dataset. If there is a positive match, this allows the conclusion that the apparatuses are correctly installed in the aircraft.

Abstract: A display panel including a driving circuit layer, multiple light emitting devices and multiple encapsulation structures is provided. The light emitting devices are disposed on the driving circuit layer, and each includes a first electrode, a light emitting pattern, a second electrode and a pixel definition layer. The light emitting pattern is disposed on the first electrode. The second electrode is disposed on the light emitting pattern. The pixel definition layer is disposed on the driving circuit layer, and has a pixel opening overlapping the first electrode. The light emitting pattern and the second electrode cover the pixel definition layer, the first electrode located in the pixel opening of the pixel definition layer and part of the driving circuit layer located outside the pixel opening of the pixel definition layer. The encapsulation structures cover the light emitting devices and each includes a first encapsulation pattern.

Abstract: A method, a unit and circuits for implementing Boolean logics based on computing-in-memory transistors. The method is implemented by using the characteristics and the read-write mode of the computing-in-memory transistor; the basic unit consists of a computing-in-memory transistor and a pull resistor; the pull resistor in the basic unit is connected in series with the transistor, and the gate of the transistor is independent; the basic units can implement sixteen Boolean logic operations through different circuit structures and voltage configuration schemes. Compared with the logic circuit structure of the conventional CMOS transistors, the present disclosure can implement more logic operations with fewer transistors, which greatly optimizes circuit density and computing speed caused by data transmission between storage units and process units.

Abstract: Method for confirming ownership of digital assets based on hash algorithm and method for tracing to a source of digital assets based on hash algorithm are provided. Entities involved in confirming the ownership of digital assets include an original user, a CA authentication center and a digital asset authentication center. The process of confirming the ownership includes generating a one-time CA certificate by the original user, authenticating the digital assets by the digital asset authorization center and the original user, generating an ownership confirming document by the original user, creating a quantum digital signature by a three-party, and the like. The method for tracing includes generating subsidiary documents in real time, constructing a unique identity for a digital asset at an accessing moment, traceability analysis, and so on.

Abstract: Disclosed is an entirely analog circuitry system for handwritten digit recognition based on computing-in-memory architecture, which a first analog circuit and a second analog circuit, the first analog circuit includes the following circuit blocks: an input driver circuit, a first resistor array with a scale of m columns and 2n rows, a first current-to-voltage conversion circuit, a first subtraction circuit, and a first activation function circuit; the second analog circuit includes the following circuit blocks: a second resistor array with a scale of n columns and 20 rows, a second current-to-voltage conversion circuit, a second subtraction circuit, a second activation function circuit, and a voltage comparison circuit. The system can eliminate a data migration problem posed by the conventional Von Neumann architecture and does not require an assistance of any digital modules, thereby enabling accurate recognition with ultra-low latency.

Abstract: A battery includes a plurality of arranged battery cells; and a pressure regulating apparatus, including a body portion and a regulating valve, where the body portion is arranged between adjacent battery cells, a gas pipeline being formed in the body portion, and the regulating valve is arranged in the gas pipeline and configured to regulate pressure in the gas pipeline so as to adjust a gap between adjacent battery cells.

Abstract: An adjustable voltage regulator circuit, including a voltage conversion circuit, a voltage conversion controller, and a clock generator, is provided. The voltage conversion circuit receives an input voltage to generate an output voltage. The voltage conversion controller detects the output voltage, compares the output voltage with a reference voltage value, and outputs an enable signal based on a comparison result to control the voltage conversion circuit to adjust the output voltage. The clock generator generates a first clock signal and a second clock signal to respectively drive the voltage conversion circuit and the voltage conversion controller. The voltage conversion controller adjusts the enable signal to gradually adjust the output voltage to a predetermined voltage range.

Abstract: Disclosed is a folding sofa bed, including a folding bed frame body, a cushion body, and a turning component. The cushion body is disposed above the folding bed frame body. The turning component is connected with the folding bed frame body and the cushion body. The turning component is capable of driving the cushion body above the folding bed frame body to turn to be below the folding bed frame body. In this application, when the folding sofa bed is unfolded, the cushion body may turn to be below the folding bed frame body through the turning component.

Abstract: A cultivation method for drip irrigation of cotton fields in saline-alkali soil is provided, belonging to the field of agricultural planting technologies. It mainly includes performing land preparation; setting a planting mode; laying tubes; performing a high frequency drip irrigation; fertilizing with water; performing intertillage; performing chemical control; and performing green prevention and control.

Abstract: A method for interfacing passenger electronic devices with passenger controllable functions involves transmitting, by a PED, a seat-based identification token to a cabin server of a passenger aircraft; requesting, by the cabin server in response to the transmission of the seat-based identification token, completion of a challenge presented by the cabin server by the user of the PED; upon successfully responding to the challenge, admitting, by the cabin server, access for the user of the PED to passenger controllable functions belonging to the passenger seat associated with the seat-based identification token transmitted by the PED; and accessing, by the user of the PED, the passenger controllable functions via remote control of the PED.

Abstract: Described herein are compounds that inhibits the membrane proximal external region (MPER) of a viral envelope (Env), as well as and compositions thereof. Further provided herein are methods for treating or preventing a viral infection comprises administering to a subject in need thereof an agent or compound that inhibits the MPER of a viral Env. In certain embodiments, the viral infection is an HIV infection.