Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

Abstract: A plasmaless dry etching method is provided. A semiconductor structure including a dielectric layer formed on a substrate is placed into an etching chamber to perform the plasmaless dry etching method. A main etchant gas, a first gas, and a precursor are introduced into the chamber. During the etching process, a passivation source is created to impede a first byproduct created by reaction of the main etchant gas and the first gas with the dielectric layer and a second byproduct is created by a gas phase reaction between the first gas, the precursor gas, and the main etchant.

Abstract: A method includes forming a first stack of alternating first semiconductor layers and first sacrificial layers over a substrate and a second stack of alternating second semiconductor layers and second sacrificial layers over the first stack; replacing the first sacrificial layers with dummy interposers, respectively; forming first source/drain epitaxy structures on opposite sides of the first semiconductor layers; forming second source/drain epitaxy structures on opposite sides of the second semiconductor layers; removing the second sacrificial layers and the dummy interposers; and forming a first gate structure wrapping around at least one of the first semiconductor layers and a second gate structure wrapping around at least one of the second semiconductor layers.

Abstract: Semiconductor devices with insulation structures and methods of fabrication are provided. A semiconductor device includes a first fin structure located over a substrate; a first gate segment located over the first fin structure; a second fin structure located over the substrate; a second gate segment located over the second fin structure; and an insulation feature located between the first fin structure and the second fin structure and located between the first gate segment and the second gate segment, wherein the insulation feature extends laterally from a first sidewall nearest the first gate segment to a second sidewall nearest the second gate segment; wherein the insulation feature includes a bottom layer and a top layer located over the bottom layer; and wherein the top layer forms an uppermost surface of the insulation feature.

Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

Abstract: Processing apparatuses and methods are provided. A processing apparatus includes an electrostatic chuck configured to hold a semiconductor wafer during a process performed on the semiconductor wafer; a first electrode configured to bias a first region of the electrostatic chuck with a first bias; and a second electrode configured to bias a second region of the electrostatic chuck with a second bias.

Abstract: A signal detector circuit includes a signal peak detector circuit, a reference voltage generation circuit, and a comparator circuit. The signal peak detector circuit is arranged to receive a plurality of differential voltage input signals, and generate a single-ended peak signal according to the plurality of differential voltage input signals. The reference voltage generation circuit is arranged to generate a single-ended reference voltage signal. The comparator circuit is arranged to receive the single-ended peak signal and the single-ended reference voltage signal, and compare the single-ended peak signal with the single-ended reference voltage signal to generate a signal detection result.

Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

Abstract: The present invention relates to a maca extract and uses thereof. The part of the maca extract extracted with polar solvent has anti-thrombotic activity, the part of the maca extract extracted with medium and low polarity solvents has anti-neutrophilic inflammatory and anti-allergic activities, the part of the maca extract extracted with low polarity solvent has anti-neutrophilic inflammatory activity and has pro-angiogenic activity.

Abstract: A signal detector circuit includes a signal peak detector circuit, a reference voltage generation circuit, and a comparator circuit. The signal peak detector circuit is arranged to receive a plurality of differential voltage input signals, and generate a single-ended peak signal according to the plurality of differential voltage input signals. The reference voltage generation circuit is arranged to generate a single-ended reference voltage signal. The comparator circuit is arranged to receive the single-ended peak signal and the single-ended reference voltage signal, and compare the single-ended peak signal with the single-ended reference voltage signal to generate a signal detection result.

Abstract: A method for performing common mode voltage re-biasing in an analog front-end circuit of a receiver, an associated common mode voltage re-biasing circuit, the receiver and an associated integrated circuit are provided. The common mode voltage re-biasing circuit may include a control circuit and multiple switchable common mode voltage re-biasing sub-circuits. The control circuit generates at least one control signal according to a command, for controlling the common mode voltage re-biasing circuit to operate in a selected circuit configuration. The multiple switchable common mode voltage re-biasing sub-circuits select a predetermined circuit configuration from a first predetermined circuit configuration and a second predetermined circuit configuration according to the at least one control signal to be the selected circuit configuration to perform common mode voltage re-biasing operations corresponding to the selected circuit configuration, respectively.

Abstract: In a method, an aluminum body is chemically treated with at least one of an alkaline solution and an acid solution. Anode-oxidization is performed on the chemically treated aluminum body to form an aluminum oxide layer. The aluminum oxide layer is treated with hot water at a temperature more than 75° C. or steam. The aluminum oxide layer after being treated with hot water or steam includes plural columnar grains, and an average width of the columnar grains is in a range from 10 nm to 100 nm.

Abstract: The present invention relates to a maca extract and uses thereof. The part of the maca extract extracted with polar solvent has anti-thrombotic activity, the part of the maca extract extracted with medium and low polarity solvents has anti-neutrophilic inflammatory and anti-allergic activities, the part of the maca extract extracted with low polarity solvent has anti-neutrophilic inflammatory activity and has pro-angiogenic activity.

Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

Abstract: A method includes forming a gate dielectric layer, forming a metal gate strip over a bottom portion of the gate dielectric layer, and performing a first etching process on the metal gate strip to remove a portion of the metal gate strip. The first etching process is performed anisotropically. After the first etching process, a second etching process is performed on the metal gate strip to remove a residue portion of the metal gate strip. The second etching process includes an isotropic etching process. A dielectric material is filled into a recess left by the etched portion and the etched residue portion of the metal gate strip.

Abstract: The present invention provides a signal detection circuit, wherein the signal detection circuit includes a sampling circuit and a determination circuit. In the operations of the signal detection circuit, the sampling circuit uses a plurality of clock signals to sample an input signal to generate a sampling result, wherein the plurality of clock signals have different phases, and frequencies of the plurality of clock signals are lower than a frequency of the input signal. The determination circuit refers to the sampling result to determine if the input signal comprises valid data, so as to determine if the input signal comes from outside a chip, wherein the chip includes the signal detection circuit.

Abstract: The present invention provides a signal detection circuit, wherein the signal detection circuit includes a sampling circuit and a determination circuit. In the operations of the signal detection circuit, the sampling circuit uses a plurality of clock signals to sample an input signal to generate a sampling result, wherein the plurality of clock signals have different phases, and frequencies of the plurality of clock signals are lower than a frequency of the input signal. The determination circuit refers to the sampling result to determine if the input signal comprises valid data, so as to determine if the input signal comes from outside a chip, wherein the chip includes the signal detection circuit.