Abstract: A memory optimization method includes identifying, within a circuit design, a memory having an arithmetic operator at an output side and/or an input side of the memory. The memory may include a read-only memory (ROM). In some examples, an input of the arithmetic operator includes a constant value. In some embodiments, the memory optimization method further includes absorbing a function of the arithmetic operator into the memory. By way of example, the absorbing the function includes modifying contents of the memory based on the function of the arithmetic operator to provide an updated memory and removing the arithmetic operator from the circuit design.

Abstract: Integrated circuits and methods relating to hardware acceleration include independent, programmable, and parallel processing units (PU) custom-adapted to process a data stream and aggregate the results to respond to a query. In an illustrative example, a data stream from a database may be divided into data blocks and allocated to a corresponding PU. Each data block may be processed by one of the PUs to generate results according to a predetermined instruction set. A concatenate unit may merge and concatenate a result of each data block together to generate an output result for the query. In some embodiments, very large database SQL queries, for example, may be accelerated by hardware PU/concatenate engines implemented in fixed ASIC or reconfigurable FPGA hardware circuitry.

Abstract: Local retiming for a circuit design includes determining, using computer hardware, a load of a synchronous circuit element within the circuit design tagged for forward retiming, traversing, using the computer hardware, each input of the load backward through the circuit design until a sequential circuit element or a primary input is reached, and adding, using the computer hardware, each synchronous circuit element encountered in the traversing to a forward retiming list. In response to determining that forward retiming criteria is met for the forward retiming list, the computer hardware modifies the circuit design by creating a new synchronous circuit element at an output of the load.

Abstract: Disclosed approaches of pipelining cascaded memory blocks include determining memory blocks combined to implement a memory in a netlist of a circuit design. A model of the memory blocks arranged in a matrix is generated and a total number of delay registers that can be inserted between an input and an output of the memory is determined based on an input latency constraint. For each column, positions of delay registers are determined between an input of the column and the output of the memory. The circuit design is modified to include the delay registers at the determined positions.

Abstract: Verifying a circuit design may include, in response to modification of the circuit design involving at least one of inserting or removing a flip-flop, determining, using computer hardware, latency change values for pins of components of the circuit design, determining, using the computer hardware, total latency for the pins of the components of the circuit design based, at least in part, upon the latency change values, and comparing, using the computer hardware, total latency of the pins of the components of the circuit design. Verifying the circuit design may also include detecting, using the computer hardware, a latency error within the circuit design based upon the comparing and generating, using the computer hardware, a notification of the latency error in the circuit design, wherein the notification specifies a type of the latency error detected.

Abstract: Circuits and method for multiplying floating point operands. An exponent adder circuit sums a first exponent and a second exponent and generates an output exponent. A mantissa multiplier circuit multiplies a first mantissa and a second mantissa and generates an output mantissa. A first conversion circuit converts the output exponent and output mantissa into a fixed point number. An accumulator circuit sums contents of an accumulation register and the fixed point number into an accumulated value and stores the accumulated value in the accumulation register.

Abstract: Certain embodiments are directed to methods of using BRD4 inhibitors for treating IgE-mediated diseases.

Abstract: Certain embodiments are directed to small molecule selective inhibitors of the BRD4 bromodomain. Compounds described herein can be used to modulate the bronchiolar NFkB-BRD4 axis, which plays a role in acute neutrophilic response to viral molecular patterns. Compounds described herein can be developed as preventive and therapeutic agents for various human diseases and conditions.

Abstract: Certain embodiments are directed to methods of treating chronic lung diseases in a subject comprising administering to a subject diagnosed with, exhibiting symptoms of, or at risk of developing a chronic lung disease a therapeutically effective amount of a BRD4 inhibitor or a CDK9 inhibitor to the subject.

Abstract: Certain embodiments are directed to methods of treating chronic lung diseases in a subject comprising administering to a subject diagnosed with, exhibiting symptoms of, or at risk of developing a chronic lung disease a therapeutically effective amount of a BRD4 inhibitor or a CDK9 inhibitor to the subject.

Abstract: In an example, a method of processing a circuit design includes: determining a first partition in a description of the circuit design having a hierarchy of design objects, the first partition including at least one design object in the hierarchy of design objects; generating a signature for the first partition; querying a database with the signature of the first partition to identify a plurality of predefined implementations of the first partition; and generating an implementation of the circuit design for a target integrated circuit (IC) based on a selected predefined implementation of the plurality of predefined implementations for the first partition.

Abstract: Compiling a circuit design includes receiving the circuit design specified in a hardware description language, detecting, using a processor, a slice of a vector within the circuit design, and determining that the slice is defined by a left slice boundary variable and a right slice boundary variable. A hardware description is generated from the circuit design using the processor by including a first shifter circuit receiving the left slice boundary variable as an input signal, a second shifter circuit receiving the right slice boundary variable as an input signal, a control signal generator coupled to the first and second shifter circuits, and an output stage. The output stage, responsive to a control signal dependent upon an output from the first shifter circuit and an output from second shifter circuit, generates an output signal including newly received values from a data signal only for bit locations of the output signal corresponding to the slice.

Abstract: A circuit for enabling a modification of an input data stream is described. The circuit comprises a first plurality of registers coupled in series; an input register of the first plurality of registers coupled to receive the input data stream; an output register of the first plurality of registers positioned at an end of the first plurality of registers; and a control circuit enabling a data value which is independent of the input data stream to be generated as an output of the circuit at a predetermined time.

Abstract: A method implemented on a data processing system for circuit synthesis is discussed. In one embodiment, the method comprises determining a net of a circuit design, the net driving one or more first loads to use a first type of routing resources and one or more second loads to use a second type of routing resources, and splitting the net into a first net and a second net, the first net driving the one or more first loads, the second net driving the one or more second loads.

Abstract: Processing a circuit design includes generating a transformation output from a transformation input for each of a plurality of transformations of a synthesis flow applied to the circuit design. For each transformation, the transformation input and the transformation output represent the circuit design. At least one circuit element is changed from the transformation input to the transformation output. For each transformation, a hardware description language representation of the transformation input and a hardware description language representation of the transformation output are generated. For each transformation, determining whether the hardware description language representation of the transformation input is equivalent to the hardware description language representation of the transformation output.

Abstract: A method implemented on a data processing system for circuit synthesis is discussed. In one embodiment, the method comprises determining a net of a circuit design, the net driving one or more first loads to use a first type of routing resources and one or more second loads to use a second type of routing resources, and splitting the net into a first net and a second net, the first net driving the one or more first loads, the second net driving the one or more second loads.

Abstract: Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a method implemented on a data processing system for circuit synthesis comprises determining a Read Only Memory (ROM) of a design of a circuit, the ROM having predefined data when the circuit is initialized, and automatically generating an initialization circuit and a Random Access Memory (RAM) to implement the ROM, the initialization circuit to load the predefined data into the RAM when the circuit is initialized.

Abstract: Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through using the extended portion of the carry chain. In one aspect of an embodiment, control/non-control loads are separated from each other through replicating the driver elements of the mixed control/non-control loads. In one aspect of an embodiment, a read only memory (ROM) is implemented using a random access memory (RAM). In one embodiment, a register at the input side of the ROM is generated through inserting a register that is clocked at an inverted clock signal or through retiming a register from the output side of the ROM.

Abstract: A method and apparatus for rapid identification of column heterogeneity in databases are disclosed. For example, the method receives data associated with a column in a database. The method computes a cluster entropy for the data as a measure of data heterogeneity and then determines whether said data is heterogeneous in accordance with the cluster entropy.

Abstract: Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through using the extended portion of the carry chain. In one aspect of an embodiment, control/non-control loads are separated from each other through replicating the driver elements of the mixed control/non-control loads. In one aspect of an embodiment, a read only memory (ROM) is implemented using a random access memory (RAM). In one embodiment, a register at the input side of the ROM is generated through inserting a register that is clocked at an inverted clock signal or through retiming a register from the output side of the ROM.