Abstract: Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through using the extended portion of the carry chain. In one aspect of an embodiment, control/non-control loads are separated from each other through replicating the driver elements of the mixed control/non-control loads. In one aspect of an embodiment, a read only memory (ROM) is implemented using a random access memory (RAM). In one embodiment, a register at the input side of the ROM is generated through inserting a register that is clocked at an inverted clock signal or through retiming a register from the output side of the ROM.

Abstract: Embodiments of the present invention disclose methods and apparatuses to reduce metastability problem related to propagation delay of reset signals in integrated circuits, with preferred applications in automatic physical synthesis for RTL (register transfer level) netlist. In an embodiment, a reset conditioning circuit is inserted into the original integrated circuit to make the reset behavior more reliable to avoid unpredictable states, especially for the de-assertion state of the reset signal. The reset conditioning circuit can provide an asynchronous reset signal output with extended duration so that all the load registers employing asynchronous reset signal will get the reset properly. Further, the reset conditioning circuit can modify the timing of the reset signal so that its de-assertion edge is synchronized with a rising clock edge.

Abstract: Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through using the extended portion of the carry chain. In one aspect of an embodiment, control/non-control loads are separated from each other through replicating the driver elements of the mixed control/non-control loads. In one aspect of an embodiment, a read only memory (ROM) is implemented using a random access memory (RAM). In one embodiment, a register at the input side of the ROM is generated through inserting a register that is clocked at an inverted clock signal or through retiming a register from the output side of the ROM.

Abstract: A method and system for routing signals through interconnect matrices in a programmable logic device such that downstream routing failures can be reduced. In one embodiment, the invention is used to improve routing in complex programmable logic devices or CPLDs, however, the invention can be applied to other programmable devices and routing resources. In routing a set of signals through an upstream interconnect matrix or PIM, the method determines a set of high priority signals. In routing the upstream PIM, the method uses a Maximum Bipartite Matching process in one embodiment to route the original signals once. The duplicated high priority signals are then routed and sent to the input array of the downstream interconnect matrix along with the originally routed signals. From the originally routed signals and the duplicate signals, the downstream interconnect matrix routes each unique signal once and only once depending on the available routing resources.