Patents by Inventor Bing-Yu Hsieh
Bing-Yu Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8429487Abstract: An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits.Type: GrantFiled: December 31, 2010Date of Patent: April 23, 2013Assignee: Mediatek Inc.Inventors: Hsiang-Hui Chang, Bing-Yu Hsieh, Jing-Hong Conan Zhan
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Patent number: 8395453Abstract: Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error or a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.Type: GrantFiled: September 23, 2008Date of Patent: March 12, 2013Assignee: Mediatek Inc.Inventors: Hsiang-Hui Chang, Bing-Yu Hsieh, Jing-Hong Conan Zhan
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Patent number: 8228128Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.Type: GrantFiled: July 19, 2010Date of Patent: July 24, 2012Assignee: Mediatek Inc.Inventors: Hsiang-Hui Chang, Ping-Ying Wang, Jing-Hong Conan Zhan, Bing-Yu Hsieh
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Patent number: 8149146Abstract: An automatic power control system, an automatic power control method, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count.Type: GrantFiled: January 18, 2011Date of Patent: April 3, 2012Assignee: Mediatek Inc.Inventors: Bing-Yu Hsieh, Ming-Jiou Yu, Kuo-Jung Lan, Shu-Hung Chou, Chih-Ching Chen, Chia-Wei Liao
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Patent number: 8031008Abstract: A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU.Type: GrantFiled: April 21, 2009Date of Patent: October 4, 2011Assignee: Mediatek Inc.Inventors: Ping-Ying Wang, Bing-Yu Hsieh, Ling-Wei Ke, Tai Yuan Yu
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Patent number: 8031007Abstract: An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.Type: GrantFiled: September 23, 2008Date of Patent: October 4, 2011Assignee: Mediatek Inc.Inventors: Hsiang-Hui Chang, Bing-Yu Hsieh, Jing-Hong Conan Zhan
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Publication number: 20110122747Abstract: An automatic power control system, an automatic power control method, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count.Type: ApplicationFiled: January 18, 2011Publication date: May 26, 2011Applicant: MEDIATEK INC.Inventors: Bing-Yu Hsieh, Ming-Jiou Yu, Kuo-Jung Lan, Shu-Hung Chou, Chih-Ching Chen, Chia-Wei Liao
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Publication number: 20110099450Abstract: An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits.Type: ApplicationFiled: December 31, 2010Publication date: April 28, 2011Inventors: Hsiang-Hui Chang, Bing-Yu Hsieh, Jing-Hong Conan Zhan
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Patent number: 7903006Abstract: An automatic power control system, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count.Type: GrantFiled: November 19, 2008Date of Patent: March 8, 2011Assignee: Mediatek Inc.Inventors: Bing-Yu Hsieh, Ming-Jiou Yu, Kuo-Jung Lan, Shu-Hung Chou, Chih-Ching Chen, Chia-Wei Liao
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Publication number: 20100277244Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.Type: ApplicationFiled: July 19, 2010Publication date: November 4, 2010Inventors: Hsiang-Hui Chang, Ping-Ying Wang, Jing-Hong Conan Zhan, Bing-Yu Hsieh
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Publication number: 20100264993Abstract: A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU.Type: ApplicationFiled: April 21, 2009Publication date: October 21, 2010Applicant: MEDIATEK INC.Inventors: Ping-Ying Wang, Bing-Yu Hsieh, Ling-Wei Ke, Tai Yuan Yu
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Patent number: 7791428Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.Type: GrantFiled: September 23, 2008Date of Patent: September 7, 2010Assignee: Mediatek Inc.Inventors: Hsiang-Hui Chang, Ping-Ying Wang, Jing-Hong Conan Zhan, Bing-Yu Hsieh
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Publication number: 20100117827Abstract: The invention provides a method for current reduction for an analog circuit in a data read-out system. First, a performance indicator, indicating a performance of the data read-out system is generated. The performance indicator is then compared with a performance threshold level to generate a switch signal. A level of a current source biasing the analog circuit is then adjusted according to the switch signal.Type: ApplicationFiled: November 12, 2008Publication date: May 13, 2010Applicant: MEDIATEK INC.Inventors: Bing-Yu Hsieh, Wei-Hsuan Tu, Chih Chuan Chen
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Patent number: 7697380Abstract: An apparatus for detecting the wobble carrier frequency of an optical disk is disclosed. The apparatus comprises an offset canceller, a binary conversion module, an adjustable band pass filter, and a frequency detection module. The offset canceller cancels the direct current offset of a first wobble signal to obtain a second wobble signal. The binary conversion module converts the second wobble signal to a binary data stream. The adjustable band pass filter passes only an adjustable frequency range of the binary data stream to generate a filtered signal, wherein the center frequency of the adjustable frequency range is sequentially adjusted. The frequency detection module then determines maximum amplitude of the filtered signal, and determines the center frequency of the adjustable frequency range according to which the filtered signal with the maximum amplitude is generated, wherein the wobble carrier frequency is the center frequency corresponding to the maximum amplitude.Type: GrantFiled: May 30, 2007Date of Patent: April 13, 2010Assignee: Mediatek Inc.Inventors: Yuh Cheng, Bing-Yu Hsieh
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Patent number: 7697399Abstract: A method for controlling a specific output power level emitted from a laser diode (LD) in an optical pick-up head unit (OPU) is disclosed. The LD is configured to provide a plurality of output power levels for accessing/recording an optical disc. The method includes: determining a specific power control value according to a first output power level, a second output power level, a first power control value of the first output power level, and the specific output power level, wherein the first output power level is less than the specific output power level and greater than the second output power level; and driving the LD to emit the specific output power level according to the specific power control value, the first power control value, and a second power control value of the second output power level.Type: GrantFiled: June 5, 2007Date of Patent: April 13, 2010Assignee: Mediatek Inc.Inventors: Ming-Jiou Yu, Chih-Ching Chen, Chia-Wei Liao, Kuo-Jung Lan, Bing-Yu Hsieh, Shu-Hung Chou, Kuan-Hua Chao, Jong-Woei Chen
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Patent number: 7693011Abstract: The invention provides a wobble detection circuit. An exemplary embodiment of the wobble detection circuit comprises an automatic gain control module, an analog to digital converter, a digital band pass filter, and a digital band pass filter. The automatic gain control module amplifies a first input signal and a second input signal detected by a pickup head to the same magnitude to obtain a first amplified signal and a second amplified signal. The adder then subtracts the second amplified signal from the first amplified signal to obtain an analog wobble signal. The analog to digital converter then converts the analog wobble signal to a first digital wobble signal. Finally, the digital band pass filter accepts frequency components of the first digital wobble signal within a pass band and rejects frequency components of the first digital wobble signal outside the pass band to obtain a second digital wobble signal.Type: GrantFiled: May 30, 2007Date of Patent: April 6, 2010Assignee: Mediatek Inc.Inventors: Yuh Cheng, Chih-Ching Chen, Chia-Wei Liao, Ming-Jiou Yu, Kuo-Jung Lan, Shu-Hung Chou, Bing-Yu Hsieh, Chia-Hua Chou
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Patent number: 7693012Abstract: The invention provides an apparatus for demodulating an Address In Pre-groove (ADIP) symbol. The ADIP symbol is carried by a wobble signal of an optical disk and comprises a series of ADIP bits permuted according to one of a plurality of permutation patterns to make up the ADIP symbol. A wobble extraction module extracts the wobble signal from the optical disk. A reference wobble generator generates a reference wobble with the same frequency and phase as a fundamental frequency and phase of a positive wobble cycle of the wobble signal. A waveform difference measurement module then measures a difference between the wobble signal and the reference wobble to obtain a series of difference measurement values respectively corresponding to the ADIP bits. A pattern matching module then compares probabilities of the permutation of the ADIP bits agreeing with each of the permutation patterns according to the difference measurement values to determine the ADIP symbol.Type: GrantFiled: May 30, 2007Date of Patent: April 6, 2010Assignee: Mediatek Inc.Inventors: Bing-Yu Hsieh, Yuh Cheng, Shu-Hung Chou, Jung-Feng Ho
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Patent number: 7613093Abstract: A pre-pit signal generating device includes: a first slicer for generating a sliced signal corresponding to a push-pull signal based on a first reference level; a duty ratio controller coupled to the first slicer for adjusting the first reference level or the push-pull signal to control a duty ratio of the sliced signal to a predetermined ratio; a reference level generator coupled to the duty ratio controller for generating a second reference level corresponding to the first reference level; and a second slicer coupled to the reference level generator for generating a first pre-pit signal corresponding to the push-pull signal based on the second reference level.Type: GrantFiled: September 28, 2005Date of Patent: November 3, 2009Assignee: MediaTek Inc.Inventors: Bing-Yu Hsieh, Chih-Ching Chen
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Publication number: 20090096539Abstract: An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.Type: ApplicationFiled: September 23, 2008Publication date: April 16, 2009Inventors: Hsiang-Hui Chang, Bing-Yu Hsieh, Jing-Hong Conan Zhan
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Publication number: 20090097609Abstract: Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error o a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.Type: ApplicationFiled: September 23, 2008Publication date: April 16, 2009Inventors: Hsiang-Hui Chang, Bing-Yu Hsieh, Jing-Hong Conan Zhan