Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for a sequence to sequence to classification model for generating recommended messages. A messaging system generates, using a sequence to sequence encoder, an embedding vector from a message being transmitted as part of a communication session, the sequence to sequence encoder having been trained based on historical message data that includes messages transmitted between users of the messaging system. The messaging system determines, based on the embedding vector, a set of candidate responses for replying to the first message, the set of candidate responses being a subset of a set of available responses. The messaging system selects, from the set of candidate responses, a set of recommended responses to the first message, and causes the set of recommended responses to be presented by a client device of a recipient user of the first message.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for generating recommended responses based on historical data. A messaging system receives a message as part of a communication session between a first client device and a second client device. The message originated from the first client device. The messaging system determines, using the message as input in a statistical model, a set of candidate responses for replying to the message. The statistical model was generated based on historical message data transmitted as part of previous communication sessions between a plurality of client devices. The set of candidate responses is a subset of a set of available candidate responses. The messaging system determines, based on a set of candidate selection rules, a subset of the candidate responses yielding a set of recommended responses to the message, and causes the set of recommended responses to be presented on the second client device.

Abstract: A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; a second pair of clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply a first pair of control signals to each the first pair of clock correction circuits, and a second pair of control signals to each of the second pair of clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.

Abstract: This disclosure provides for systems and methods that generate personalized electronic messages for members of a networked communication service. The personalized electronic messages are generated according to commonalities between member profiles. In one approach, an electronic message template is referenced based on the commonalities. The electronic message template is populated with member profile attribute values selected from the member profiles. In another approach, a long-short term memory (LSTM) recurrent neural network (RNN) is used to generate the electronic messages. Under this approach, a sequence-to-sequence model is trained using previous electronic messages labeled with one or more member profile attributes and/or member profile attribute values. When provided with one or more member profile attribute values associated with matching member profiles, the LSTM RNN outputs a relevant and appropriate electronic message designed to create an interest in the recipient of the electronic message.

Abstract: A data driver includes pre-driver circuitry coupled to a digital-to-analog converter (DAC) via a plurality of bit lines. The pre-driver circuitry is configured to receive a plurality of first voltages corresponding to respective bits of a digital codeword. Each of the first voltages may have one of a first voltage value or a ground potential based on a value of the corresponding bit. The pre-driver circuitry is further configured to drive a plurality of second voltages onto the plurality of bit lines, respectively, by switchably coupling each of the bit lines to ground or a voltage rail based at least in part on the voltage values of the plurality of first voltages. The voltage rail provides a second voltage value that is greater than the first voltage value. The DAC converts the plurality of second voltages to an electrical signal which is an analog representation of the digital codeword.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for a sequence to sequence to classification model for generating recommended messages. A messaging system generates, using a sequence to sequence encoder, an embedding vector from a message being transmitted as part of a communication session, the sequence to sequence encoder having been trained based on historical message data that includes messages transmitted between users of the messaging system. The messaging system determines, based on the embedding vector, a set of candidate responses for replying to the first message, the set of candidate responses being a subset of a set of available responses. The messaging system selects, from the set of candidate responses, a set of recommended responses to the first message, and causes the set of recommended responses to be presented by a client device of a recipient user of the first message.

Abstract: Techniques for generating diverse smart replies using a synonym hierarchy are disclosed herein. A computer system may detect that a first set of one or more messages having first content has been transmitted from a first computing device of a first user to a second computing device of a second user, determine a plurality of candidate replies based on the first content of the first set of one or more messages, and then select a plurality of smart replies from the plurality of candidate replies using a hierarchical graph data structure and at least one diversity rule. The selecting of the plurality of smart replies comprises omitting at least one of the plurality of candidate replies from selection based on the at least one diversity rule, which limits a number of the plurality of smart replies that have a common parent node.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for generating personalized smart responses. A messaging system receives a message transmitted as part of a communication session between a first user and a second user and determines a set of candidate responses for replying to the message. The messaging system filters the set of candidate responses based on a personalized vocabulary for the first user, yielding a set of personalized candidate responses. The personalized vocabulary for the first user is determined based on member profile data associated with the first user. The messaging system determines, based on a set of personalized candidate selection rules, a subset of the candidate responses, yielding a set of recommended responses to the message, and causes the set of recommended responses to be presented on the second client device.

Abstract: The present disclosure relates to a method and a device for controlling information transmission and a smart terminal. The method includes: receiving an instruction for outputting information sent by a near field communication (NFC) chip, an information output function of the NFC chip being in a disabled state and information to be outputted being in an unavailable state; performing authentication of an identity of a user who triggers the information output; and if it is determined that the authentication of the identity is passed, enabling the information output function of the NFC chip and setting the information to be outputted as in an available state, such that the NFC chip can output the information. In the present disclosure, the information transmission through NFC can be more safe and reliable.

Abstract: Method and system for enriching a knowledge graph are described. The knowledge graph enrichment system provides a way of generating candidates for a new node ready to be folded into the existing graph, and also a new way of connecting nodes via semantic equivalence inferred via the proposed approach. The technical problem of inferring the sematic equivalent entities and relating them automatically in the knowledge graph is addressed by providing the methodology that utilizes neural machine translation via round trip translations through one or more bridging languages. A bridging language is a natural or an artificial morphologically-rich language.

Abstract: A method for manufacturing high-purity aluminum hydroxide and alumina material is disclosed, which includes the steps of: reacting aluminum metal with a mixture of organic base and water to form aluminum hydroxide suspension; removing water by filtration to form aluminum hydroxide slurry, and for manufacturing alumina material, further drying/baking the slurry to form aluminum oxide powders. The method is amenable to mass production of high-purity aluminum hydroxide and aluminum oxide containing total silica and non-aluminum metal impurities less than 0.005% and having a bulk density higher than 3.0 g/cc. In addition, the invention also provides high-purity aluminum hydroxide and aluminum oxide prepared by using the method disclosed and bulk products prepared therefrom.

Abstract: Provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first N well (22), a first P well (24) and a channel region shallow trench isolating structure (42) are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (52); performing photoetching and ion injection to form a second N well (32) in the first N well and form a second P well (34) in the first P well; forming a polysilicon gate (62) and a gate oxide layer on the surface of the wafer; and photoetching and injecting N-type ions to form a drain electrode (72) and a source electrode (74).

Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for generating recommended responses based on historical data. A messaging system receives a message as part of a communication session between a first client device and a second client device. The message originated from the first client device. The messaging system determines, using the message as input in a statistical model, a set of candidate responses for replying to the message. The statistical model was generated based on historical message data transmitted as part of previous communication sessions between a plurality of client devices. The set of candidate responses is a subset of a set of available candidate responses. The messaging system determines, based on a set of candidate selection rules, a subset of the candidate responses yielding a set of recommended responses to the message, and causes the set of recommended responses to be presented on the second client device.

Abstract: A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; a second pair of clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply a first pair of control signals to each the first pair of clock correction circuits, and a second pair of control signals to each of the second pair of clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.

Abstract: The present invention relates to a tantalum wire for anode lead of tantalum capacitors, characterized in that the cross section of the tantalum wire is approximate rectangular or regular rectangular. The present invention also relates to a process for manufacturing the tantalum wire, comprising the steps of: providing feedstock tantalum wire; subjecting the feedstock tantalum wire to heat treatment; subjecting the heat treated tantalum wire to surface pretreatment to form an oxide membrane on the surface-pretreated tantalum wire; rolling the surface-pretreated tantalum wire by lubricating with lubricant oil to make the cross section of the rolled tantalum wire being approximate rectangular or regular rectangular; subjecting the tantalum wire to final annealing.

Abstract: Techniques for identifying multilingual cognates and using the multilingual cognates are provided. In one technique, multilingual cognates identified from multiple user profiles are used to train one or more translation models. In another technique, multilingual cognates identified from a single user's profile are used to translate text provided by that user. In another technique, multilingual cognates from a single user are used to align sentences in one language to sentences in another language and the aligned sentences are used to train a language model. In another technique, multilingual cognates identified from multiple user profiles are used to expand search queries. In another technique, multilingual cognates identified from multiple user profiles are used to translate other users' profiles into a target language so that users associated with a source language are viewing the other users' profiles.

Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).

Abstract: Provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first N well (22), a first P well (24) and a channel region shallow trench isolating structure (42) are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (52); performing photoetching and ion injection to form a second N well (32) in the first N well and form a second P well (34) in the first P well; forming a polysilicon gate (62) and a gate oxide layer on the surface of the wafer; and photoetching and injecting N-type ions to form a drain electrode (72) and a source electrode (74).

Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).