Abstract: Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

Abstract: A dishwasher (100) for washing dirty articles comprising: a rotating rack (1) configured to rotate counter-clockwise at a user-defined speed of 1 round per minute or ½ round per minute; a spray system (104) configured to dispense a jet stream of high speed water using a plurality of nozzles (106a-106n) from the bottom as well as top of the dirty articles placed on the rotating rack (1); a washing chamber (1b) that may be designed to enable washing of the dirty articles placed upon the rotating rack (1) using the spray system (104), wherein the washing chamber (1b) uses recirculating water; and a rinsing chamber (1c) that may be designed to rinse the washed articles with clean water supplied directly from a house water source; wherein a partition wall (29) between the washing chamber (1b) and the rinsing chamber (1c) prevents splash of water used in the respective chamber.

Abstract: A dishwasher (100) for washing dirty articles comprising: a rotating rack (1) configured to rotate counter-clockwise at a user-defined speed of 1 round per minute or 1/2 round per minute; a spray system (104) configured to dispense a jet stream of high speed water using a plurality of nozzles (106a-106n) from the bottom as well as top of the dirty articles placed on the rotating rack (1); a washing chamber (1b) that may be designed to enable washing of the dirty articles placed upon the rotating rack (1) using the spray system (104), wherein the washing chamber (1b) uses recirculating water; and a rinsing chamber (1c) that may be designed to rinse the washed articles with clean water supplied directly from a house water source; wherein a partition wall (29) between the washing chamber (1b) and the rinsing chamber (1c) prevents splash of water used in the respective chamber.

Abstract: A component for a bit driving tool is taught having a mid-chamber telescopically received in an outer chamber, a bit storage chamber formed in the mid-chamber and surrounding and rotatable about a central bore, a central rod axially movable through the central bore when the mid-chamber is telescopically retracted into the outer chamber and a flexible arm comprising a magnetic end, movable into and out of axial alignment with the central bore. Telescopic extension of the mid-chamber out of the outer chamber positions the magnetic end of the flexible arm to magnetically connect with a rear end of a bit stored in the bit storage chamber and telescopic retraction of the component moves the flexible arm and the magnetically connected bit radially into the central bore and wherein further telescope retraction of the component pushes the bit axially through and out of the component. A locking tip for use with a bit driving unit is also taught.

Abstract: Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.

Abstract: A processor includes a translation lookaside buffer (TLB) to store a TLB entry, wherein the TLB entry comprises a first set of valid bits to identify if the first TLB entry corresponds to a virtual address from a memory access request, wherein the valid bits are set based on a first page size associated with the TLB entry from a first set of different page sizes assigned to a first probe group; and a control circuit to probe the TLB for each page size of the first set of different page sizes assigned to the first probe group in a single probe cycle to determine if the TLB entry corresponds to the virtual address from the memory access request.

Abstract: An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.

Abstract: Systems, methods, and apparatuses relating to circuitry to accelerate store processing are described. In one embodiment, a processor includes a (e.g.

Abstract: Examples described herein relate to a computing system supporting custom page sized ranges for an application to map contiguous memory regions instead of many smaller sized pages. An application can request a custom range size. An operating system can allocate a contiguous physical memory region to a virtual address range by specifying a custom range sizes that are larger or smaller than the normal general page sizes. Virtual-to-physical address translation can occur using an address range circuitry and translation lookaside buffer in parallel. The address range circuitry can determine if a custom entry is available to use to identify a physical address translation for the virtual address. Physical address translation can be performed by transforming the virtual address in some examples.

Abstract: A snapshot prefetcher to perform snapshot prefetching to improve performance of snapshot read operations. An apparatus embodiment includes a snapshot read tracking circuitry to track snapshot read requests made by a first processor core to read a plurality of cache lines, and to detect a snapshot read access stream based on the tracked snapshot read requests. A snapshot prefetch issuing circuitry of the apparatus to issue, based on the detected snapshot read access stream, one or more snapshot prefetch requests, including a first snapshot prefetch request to prefetch data from a first cache line stored in, and owned exclusively by, a first storage location outside the first processor core. The snapshot prefetch issuing circuitry further to store the prefetched data in a second storage location within the first processor core, wherein after the prefetch, exclusive ownership of the first cache line is to remain with the first storage location.

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

Abstract: The present invention relates generally to a method of treating a neoplastic condition and to agents useful for same. More particularly, the present invention is directed to a method of facilitating the treatment of a solid tumour in a localised manner via the co-administration of particulate material and a cellular toxin. The method of the present invention is useful in a range of therapeutic treatments including the treatment of primary and metastatic tumours.

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

Abstract: The present invention relates generally to a method of treating a neoplastic condition and to agents useful for same. More particularly, the present invention is directed to a method of facilitating the treatment of a solid tumor in a localized manner via the co-administration of particulate material and a cellular toxin. The method of the present invention is useful in a range of therapeutic treatments including the treatment of primary and metastatic tumors.

Abstract: A processor includes a translation lookaside buffer (TLB) to store a TLB entry, wherein the TLB entry comprises a first set of valid bits to identify if the first TLB entry corresponds to a virtual address from a memory access request, wherein the valid bits are set based on a first page size associated with the TLB entry from a first set of different page sizes assigned to a first probe group; and a control circuit to probe the TLB for each page size of the first set of different page sizes assigned to the first probe group in a single probe cycle to determine if the TLB entry corresponds to the virtual address from the memory access request.

Abstract: An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.

Abstract: The present invention relates generally to a method of treating a neoplastic condition and to agents useful for same. More particularly, the present invention is directed to a method of facilitating the treatment of a solid tumour in a localised manner via the co-administration of particulate material and a cellular toxin. The method of the present invention is useful in a range of therapeutic treatments including the treatment of primary and metastatic tumours.

Abstract: A method and composition for treatment of bacterial infections caused by gram negative or gram positive bacteria such as Staphylococcus aureus, Rhodococcus equi, Mycobacterium tuberculosis, Escherichia coli, Klebsiella pneumoniae, Klebsiella oxytoca, Pseudomonas aeruginosa, Haemophilus influenzae, Proteus mirabilis, Enterobacter species, Serratia marcescens as well as those caused by Burkholderia cepacia, Stenotrophomonas maltophilia, Alcaligenes xylosoxidans, and multidrug resistant Pseudomonas aeruginosa, using a formulation containing gallium (III), in a pharmaceutically acceptable salt or complex thereof.