Patents by Inventor Binh Pham

Binh Pham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11370103
    Abstract: A component for a bit driving tool is taught having a mid-chamber telescopically received in an outer chamber, a bit storage chamber formed in the mid-chamber and surrounding and rotatable about a central bore, a central rod axially movable through the central bore when the mid-chamber is telescopically retracted into the outer chamber and a flexible arm comprising a magnetic end, movable into and out of axial alignment with the central bore. Telescopic extension of the mid-chamber out of the outer chamber positions the magnetic end of the flexible arm to magnetically connect with a rear end of a bit stored in the bit storage chamber and telescopic retraction of the component moves the flexible arm and the magnetically connected bit radially into the central bore and wherein further telescope retraction of the component pushes the bit axially through and out of the component. A locking tip for use with a bit driving unit is also taught.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: June 28, 2022
    Assignee: THUNDERCHUCK INNOVATIONS INC.
    Inventors: Binh Pham, Alan Kent Farrell
  • Publication number: 20210405974
    Abstract: Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.
    Type: Application
    Filed: June 27, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Menachem Adelman, Robert Valentine, Barukh Ziv, Amit Gradstein, Simon Rubanovich, Zeev Sperber, Mark J. Charney, Christopher J. Hughes, Alexander F. Heinecke, Evangelos Georganas, Binh Pham
  • Patent number: 11055232
    Abstract: A processor includes a translation lookaside buffer (TLB) to store a TLB entry, wherein the TLB entry comprises a first set of valid bits to identify if the first TLB entry corresponds to a virtual address from a memory access request, wherein the valid bits are set based on a first page size associated with the TLB entry from a first set of different page sizes assigned to a first probe group; and a control circuit to probe the TLB for each page size of the first set of different page sizes assigned to the first probe group in a single probe cycle to determine if the TLB entry corresponds to the virtual address from the memory access request.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: David Pardo Keppel, Binh Pham
  • Patent number: 10860244
    Abstract: An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Binh Pham, Christopher B. Wilkerson, Alaa R. Alameldeen, Zeshan A. Chishti, Zhe Wang
  • Patent number: 10754782
    Abstract: Systems, methods, and apparatuses relating to circuitry to accelerate store processing are described. In one embodiment, a processor includes a (e.g.
    Type: Grant
    Filed: March 30, 2019
    Date of Patent: August 25, 2020
    Assignee: INTEL CORPORATION
    Inventors: Binh Pham, Chen Dan
  • Publication number: 20200233814
    Abstract: Examples described herein relate to a computing system supporting custom page sized ranges for an application to map contiguous memory regions instead of many smaller sized pages. An application can request a custom range size. An operating system can allocate a contiguous physical memory region to a virtual address range by specifying a custom range sizes that are larger or smaller than the normal general page sizes. Virtual-to-physical address translation can occur using an address range circuitry and translation lookaside buffer in parallel. The address range circuitry can determine if a custom entry is available to use to identify a physical address translation for the virtual address. Physical address translation can be performed by transforming the virtual address in some examples.
    Type: Application
    Filed: February 10, 2020
    Publication date: July 23, 2020
    Inventors: Farah E. FARGO, Mitchell DIAMOND, David KEPPEL, Samantika S. SURY, Binh PHAM, Shobha VISSAPRAGADA
  • Publication number: 20200104259
    Abstract: A snapshot prefetcher to perform snapshot prefetching to improve performance of snapshot read operations. An apparatus embodiment includes a snapshot read tracking circuitry to track snapshot read requests made by a first processor core to read a plurality of cache lines, and to detect a snapshot read access stream based on the tracked snapshot read requests. A snapshot prefetch issuing circuitry of the apparatus to issue, based on the detected snapshot read access stream, one or more snapshot prefetch requests, including a first snapshot prefetch request to prefetch data from a first cache line stored in, and owned exclusively by, a first storage location outside the first processor core. The snapshot prefetch issuing circuitry further to store the prefetched data in a second storage location within the first processor core, wherein after the prefetch, exclusive ownership of the first cache line is to remain with the first storage location.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Ren Wang, Lawrence C. Stewart, Binh Pham, Andrew Herdrich, Venkata Krishnan, Anil Vasudevan, Joseph Nuzman, Tsung-Yuan Tai
  • Publication number: 20200081718
    Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Inventors: Christopher Wilkerson, Binh Pham, Patrick Lu, Jared Warner Stark, IV
  • Patent number: 10521236
    Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Christopher Wilkerson, Binh Pham, Patrick Lu, Jared Warner Stark, IV
  • Publication number: 20190365901
    Abstract: The present invention relates generally to a method of treating a neoplastic condition and to agents useful for same. More particularly, the present invention is directed to a method of facilitating the treatment of a solid tumour in a localised manner via the co-administration of particulate material and a cellular toxin. The method of the present invention is useful in a range of therapeutic treatments including the treatment of primary and metastatic tumours.
    Type: Application
    Filed: July 30, 2019
    Publication date: December 5, 2019
    Inventors: Brian Stanley Hawkett, Trevor William Hambley, Nicole Sarah Bryce, Thi Thuy Binh Pham, Nirmesh Jain
  • Publication number: 20190303162
    Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Christopher Wilkerson, Binh Pham, Patrick Lu, Jared Warner Stark, IV
  • Patent number: 10376589
    Abstract: The present invention relates generally to a method of treating a neoplastic condition and to agents useful for same. More particularly, the present invention is directed to a method of facilitating the treatment of a solid tumor in a localized manner via the co-administration of particulate material and a cellular toxin. The method of the present invention is useful in a range of therapeutic treatments including the treatment of primary and metastatic tumors.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: August 13, 2019
    Assignee: The University of Sydney
    Inventors: Brian Stanley Hawkett, Trevor William Hambley, Nicole Sarah Bryce, Thi Thuy Binh Pham, Nirmesh Jain
  • Publication number: 20190227947
    Abstract: A processor includes a translation lookaside buffer (TLB) to store a TLB entry, wherein the TLB entry comprises a first set of valid bits to identify if the first TLB entry corresponds to a virtual address from a memory access request, wherein the valid bits are set based on a first page size associated with the TLB entry from a first set of different page sizes assigned to a first probe group; and a control circuit to probe the TLB for each page size of the first set of different page sizes assigned to the first probe group in a single probe cycle to determine if the TLB entry corresponds to the virtual address from the memory access request.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: David Pardo Keppel, Binh Pham
  • Publication number: 20190042145
    Abstract: An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.
    Type: Application
    Filed: December 26, 2017
    Publication date: February 7, 2019
    Inventors: Binh PHAM, Christopher B. WILKERSON, Alaa R. ALAMELDEEN, Zeshan A. CHISHTI, Zhe WANG
  • Publication number: 20180117160
    Abstract: The present invention relates generally to a method of treating a neoplastic condition and to agents useful for same. More particularly, the present invention is directed to a method of facilitating the treatment of a solid tumour in a localised manner via the co-administration of particulate material and a cellular toxin. The method of the present invention is useful in a range of therapeutic treatments including the treatment of primary and metastatic tumours.
    Type: Application
    Filed: December 22, 2017
    Publication date: May 3, 2018
    Inventors: Brian Stanley Hawkett, Trevor William Hambley, Nicole Sarah Bryce, Thi Thuy Binh Pham, Nirmesh Jain
  • Patent number: 9539233
    Abstract: A method and composition for treatment of bacterial infections caused by gram negative or gram positive bacteria such as Staphylococcus aureus, Rhodococcus equi, Mycobacterium tuberculosis, Escherichia coli, Klebsiella pneumoniae, Klebsiella oxytoca, Pseudomonas aeruginosa, Haemophilus influenzae, Proteus mirabilis, Enterobacter species, Serratia marcescens as well as those caused by Burkholderia cepacia, Stenotrophomonas maltophilia, Alcaligenes xylosoxidans, and multidrug resistant Pseudomonas aeruginosa, using a formulation containing gallium (III), in a pharmaceutically acceptable salt or complex thereof.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: January 10, 2017
    Assignee: Aridis Pharmaceuticals Inc.
    Inventors: Satoshi Ohtake, Vu Truong-Le, David Lechuga-Ballesteros, Luisa Yee, Binh Pham, Russell Martin, Atul Saxena
  • Publication number: 20160339579
    Abstract: A component for a bit driving tool is taught having a mid-chamber telescopically received in an outer chamber, a bit storage chamber formed in the mid-chamber and surrounding and rotatable about a central bore, a central rod axially movable through the central bore when the mid-chamber is telescopically retracted into the outer chamber and a flexible arm comprising a magnetic end, movable into and out of axial alignment with the central bore. Telescopic extension of the mid-chamber out of the outer chamber positions the magnetic end of the flexible arm to magnetically connect with a rear end of a bit stored in the bit storage chamber and telescopic retraction of the component moves the flexible arm and the magnetically connected bit radially into the central bore and wherein further telescope retraction of the component pushes the bit axially through and out of the component. A locking tip for use with a bit driving unit is also taught.
    Type: Application
    Filed: January 7, 2015
    Publication date: November 24, 2016
    Inventors: Binh PHAM, Alan Kent FARRELL
  • Patent number: 9298868
    Abstract: A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: March 29, 2016
    Assignee: NVIDIA Corporation
    Inventors: Vikas Agrawal, Shrivathsa Bhargavravichandran, Binh Pham, Jay Chen, Sridhar Krishnamurthy, Umang Shah, Chi Keung Lee
  • Publication number: 20150202752
    Abstract: A component of a bit driving tool is presented, having a mid-chamber, telescopically received in an outer chamber. A bit storage chamber is formed in the mid-chamber, surrounding and rotatable about a central. A central rod extends through and out of the outer chamber. A dual lever arm comprising a first magnetic end and a second end is pivotably connected to the central rod such that the dual lever arm pivots into and out of axial alignment with the central bore. Telescopic extension of the mid-chamber out of the outer chamber positions the dual lever arm to magnetically connect with a rear end of a bit stored in the bit storage chamber and telescopic retraction of the component pivots the bit radially inwardly into the central chamber and wherein further telescope retraction of the component pushes the bit through the central chamber until the bit extends out of the component.
    Type: Application
    Filed: January 7, 2015
    Publication date: July 23, 2015
    Inventors: Alan Kent FARRELL, Binh PHAM
  • Publication number: 20150037252
    Abstract: The present invention relates generally to a method of treating a neoplastic condition and to agents useful for same. More particularly, the present invention is directed to a method of facilitating the treatment of a solid tumor in a localised manner via the co-administration of particulate material and a cellular toxin. The method of the present invention is useful in a range of therapeutic treatments including the treatment of primary and metastatic tumors.
    Type: Application
    Filed: April 20, 2012
    Publication date: February 5, 2015
    Applicant: THE UNIVERSITY OF SYDNEY
    Inventors: Brian Stanley Hawkett, Trevor William Hambley, Nicole Sarah Bryce, Thi Thuy Binh Pham, Nirmesh Jain