Abstract: Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.

Abstract: Methods and apparatus relating to a universal core to accelerator communication architecture for enhanced performance and/or programmability are described. In an embodiment, a sending agent is coupled to a processor core and a receiving agent is coupled to a hardware accelerator device. Memory store data corresponding to a request from the processor core. The sending agent and the receiving agent maintain a communication channel to facilitate communication between the processor core and the hardware accelerator device in response to the request. Other embodiments are also disclosed and claimed.

Abstract: Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.

Abstract: This application describes cells, systems, and molecular engineering methods using CRISPR/Cas complexes for targeted activation of endogenous master transcriptional regulatory elements (MTRE) such as PRDM1, XBP1 and IRF4, to generate high productivity antibody production in production cell lines such as CHO and NSO cells. These incorporate the inclusion of the Cas accessory proteins, design of multiple guide RNAs (gRNA), and unique multiplexing of these components using, e.g., lentiviral transfection to induce increased transcription and translation of antibody genes under the control of the MTRE. The methods result in synergies increasing monoclonal antibody production by these modified cell lines. While a significant increase in productivity is demonstrated by this method of activation, further increase in productivity can be accomplished by genetic transfer of additional copies of MTREs.

Abstract: Examples described herein relate to a computing system supporting custom page sized ranges for an application to map contiguous memory regions instead of many smaller sized pages. An application can request a custom range size. An operating system can allocate a contiguous physical memory region to a virtual address range by specifying a custom range sizes that are larger or smaller than the normal general page sizes. Virtual-to-physical address translation can occur using an address range circuitry and translation lookaside buffer in parallel. The address range circuitry can determine if a custom entry is available to use to identify a physical address translation for the virtual address. Physical address translation can be performed by transforming the virtual address in some examples.

Abstract: This invention provides methods and systems for enhancement of protein production from mammalian cell lines in a drug inducible manner. The methods described herein can be used to generate a protein production cell line wherein the gene coding the protein product of interest is inserted into specific safe harbor loci (SHL) within the cell's genome and the gene copy number is induced to amplify by the use of an antibiotic inducer. The method enables for the conditional activation of the drug inducible transposase. The drug inducible gene amplification method described herein effectively functions as a molecular dial: combining drug-inducible homologous recombination and conditional gene activation to fine-tune gene amplification in mammalian systems.

Abstract: Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

Abstract: A component for a bit driving tool is taught having a mid-chamber telescopically received in an outer chamber, a bit storage chamber formed in the mid-chamber and surrounding and rotatable about a central bore, a central rod axially movable through the central bore when the mid-chamber is telescopically retracted into the outer chamber and a flexible arm comprising a magnetic end, movable into and out of axial alignment with the central bore. Telescopic extension of the mid-chamber out of the outer chamber positions the magnetic end of the flexible arm to magnetically connect with a rear end of a bit stored in the bit storage chamber and telescopic retraction of the component moves the flexible arm and the magnetically connected bit radially into the central bore and wherein further telescope retraction of the component pushes the bit axially through and out of the component. A locking tip for use with a bit driving unit is also taught.

Abstract: Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.

Abstract: A processor includes a translation lookaside buffer (TLB) to store a TLB entry, wherein the TLB entry comprises a first set of valid bits to identify if the first TLB entry corresponds to a virtual address from a memory access request, wherein the valid bits are set based on a first page size associated with the TLB entry from a first set of different page sizes assigned to a first probe group; and a control circuit to probe the TLB for each page size of the first set of different page sizes assigned to the first probe group in a single probe cycle to determine if the TLB entry corresponds to the virtual address from the memory access request.

Abstract: An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.

Abstract: Systems, methods, and apparatuses relating to circuitry to accelerate store processing are described. In one embodiment, a processor includes a (e.g.

Abstract: Examples described herein relate to a computing system supporting custom page sized ranges for an application to map contiguous memory regions instead of many smaller sized pages. An application can request a custom range size. An operating system can allocate a contiguous physical memory region to a virtual address range by specifying a custom range sizes that are larger or smaller than the normal general page sizes. Virtual-to-physical address translation can occur using an address range circuitry and translation lookaside buffer in parallel. The address range circuitry can determine if a custom entry is available to use to identify a physical address translation for the virtual address. Physical address translation can be performed by transforming the virtual address in some examples.

Abstract: A snapshot prefetcher to perform snapshot prefetching to improve performance of snapshot read operations. An apparatus embodiment includes a snapshot read tracking circuitry to track snapshot read requests made by a first processor core to read a plurality of cache lines, and to detect a snapshot read access stream based on the tracked snapshot read requests. A snapshot prefetch issuing circuitry of the apparatus to issue, based on the detected snapshot read access stream, one or more snapshot prefetch requests, including a first snapshot prefetch request to prefetch data from a first cache line stored in, and owned exclusively by, a first storage location outside the first processor core. The snapshot prefetch issuing circuitry further to store the prefetched data in a second storage location within the first processor core, wherein after the prefetch, exclusive ownership of the first cache line is to remain with the first storage location.

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

Abstract: A processor includes a translation lookaside buffer (TLB) to store a TLB entry, wherein the TLB entry comprises a first set of valid bits to identify if the first TLB entry corresponds to a virtual address from a memory access request, wherein the valid bits are set based on a first page size associated with the TLB entry from a first set of different page sizes assigned to a first probe group; and a control circuit to probe the TLB for each page size of the first set of different page sizes assigned to the first probe group in a single probe cycle to determine if the TLB entry corresponds to the virtual address from the memory access request.

Abstract: An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.