Abstract: This invention provides methods and compositions to preserve bioactive materials in a matrix of powder particles. Methods provide high-pressure gas spraying and/or near supercritical spraying of formulations followed by drying in a stream of conditioned gas to form stable powder particles containing bioactive materials.

Abstract: An apparatus, system, and method for speeding up data transfers while reducing bus contention during repeated consecutive read-write operations. By reducing the length of time during which selected data pulses are driven on the memory bus, a higher percentage of usage of the memory bus may be attained without increasing the likelihood of bus contention and resulting degradation or damage to the memory system. The selected data pulse is preferably the write data pulse driven on the memory bus by the memory controller. A zero bus turnaround protocol may be implemented. The memory controller may include interface circuitry and write control circuitry that outputs an associated control signal to a three-state buffer. The three-state buffer, after being enabled by the associated control signal, drives write data on a data line of a memory bus. The turn-on delay associated with the three-state buffer exceeds the turn-off delay also associated with the three-state buffer.

Abstract: An apparatus, system, and method for speeding up data transfers while reducing bus contention during repeated consecutive read-write operations. By reducing the length of time during which selected data pulses are driven on the memory bus, a higher percentage of usage of the memory bus may be attained without increasing the likelihood of bus contention and resulting degradation or damage to the memory system. The selected data pulse is preferably the write data pulse driven on the memory bus by the memory controller. A zero bus turnaround protocol may be implemented. The memory controller may include interface circuitry and write control circuitry that outputs an associated control signal to a three-state buffer. The three-state buffer, after being enabled by the associated control signal, drives write data on a data line of a memory bus. The turn-on delay associated with the three-state buffer exceeds the turn-off delay also associated with the three-state buffer.

Abstract: An apparatus, system, and method for speeding up data transfers while reducing bus contention during repeated consecutive read-write operations. By reducing the length of time during which selected data pulses are driven on the memory bus, a higher percentage of usage of the memory bus may be attained without increasing the likelihood of bus contention and resulting degradation or damage to the memory system. The selected data pulse is preferably the write data pulse driven on the memory bus by the memory controller. A zero bus turnaround protocol may be implemented. The memory controller may include interface circuitry and write control circuitry that outputs an associated control signal to a three-state buffer. The three-state buffer, after being enabled by the associated control signal, drives write data on a data line of a memory bus. The turn-on delay associated with the three-state buffer exceeds the turn-off delay also associated with the three-state buffer.

Abstract: A method and apparatus for managing a buffer memory in a packet switch that is shared between multiple ports in a network system. The apparatus comprises a plurality of slow data port interfaces configured to transmit data at a first data rate between a slow data port and the buffer memory and a plurality of fast data port interfaces configured to transmit data at a second data rate between a fast data port and the buffer memory. A first level arbiter is coupled to the plurality of slow data port interfaces. The first level arbiter chooses an access request of one the slow data ports and outputs the access request. A second level arbiter is coupled to the plurality of fast data port interfaces and to the output of the first level arbiter. The second level arbiter chooses an access request from among a plurality access requests from the fast data port interfaces and the access request from the first level arbiter, and forwards the chosen access request to the memory.

Abstract: A method and apparatus for controlling access to a shared memory in a network system is described. The apparatus includes at least one fast port interface circuit, each comprising a fast input port interface configured to sequentially receive data, address, and command information from a network client at a first data rate in segments of a first width. Each fast input port interface comprises a fast interface register configured to temporarily store the data and address information. Each fast input port interface further comprises a command decode circuit configured to receive the command information and, in response, sequentially store the segments of data and address information in the fast interface register until the fast interface register is full, the fast interface register further configured to be read out in parallel to the shared memory.