Abstract: An apparatus and system are described to provide an in-memory computing non-volatile flash memory cell array used in a neural network. Each cell includes a Resistive RAM memory (RRAM) and a physical resistor formed from a high resistive material. The RRAM is programmed to either an on or off state in which the resistance is respectively significantly less or more than the resistor to permit the RRAM to act as a switch and allow for in-situ training. Multi-bit RRAM cells contain multiple RRAMs, each of which is connected to a resistor having a different resistance and read using the same input line. The resistors are formed from the same material as the resistor in the analog-to-digital converter used to read the array.

Abstract: The present disclosure relates to a method of programming resistive memory cells of a resistive memory, the method comprising: applying, by a programming circuit based on a first target resistive state, an initial resistance modification to a first cell of the resistive memory to change its resistance from an initial resistive state to a first new resistance; comparing, by the programming circuit, the first new resistance of the first cell with a resistance range of the first target resistive state and with a target resistance range associated with the first target resistive state; and if it is determined that the first new resistance is outside the resistance range of the target resistive state and inside the target resistance range, applying by the programming circuit one or more further resistance modifications to the first cell to increase or decrease its resistance.

Abstract: The present disclosure relates to a method of programming resistive memory cells of a resistive memory, the method comprising: applying, by a programming circuit based on a first target resistive state, an initial resistance modification to a first cell of the resistive memory to change its resistance from an initial resistive state to a first new resistance; comparing, by the programming circuit, the first new resistance of the first cell with a resistance range of the first target resistive state and with a target resistance range associated with the first target resistive state; and if it is determined that the first new resistance is outside the resistance range of the target resistive state and inside the target resistance range, applying by the programming circuit one or more further resistance modifications to the first cell to increase or decrease its resistance.

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

Abstract: A method for a memory redundancy, including a memory array typically having a plurality of columns (e.g., bit lines) of memory cells, and identifying a particular (e.g., defective) column of the memory array and further defining a redundancy window by selecting a group of adjacent columns including the defective column. The number of columns in the group of selected columns may be equal to the number of columns in a redundancy array that is coupled to the memory array. The redundancy array is used for storing information that would have been otherwise stored in the memory cells in the redundancy window. The selected group includes at least one column on one side of the defective column and another column on the other side of the defective column. Typically, there will be multiple columns on each side of the defective column.

Abstract: A method for controlling gate voltage in a memory device is described. The method includes providing a circuit that is adapted to be coupled with the memory device. The circuit is for generating a reference voltage. The method further includes utilizing the reference voltage provided by the circuit to apply a voltage at a gate of the memory device. The voltage has a value corresponding to a temperature of the memory device. The method also includes retaining a proportional relationship between the reference voltage and the temperature of the memory device, regardless of the change in the temperature of the memory device. The reference voltage provides a substantially constant programming time for the memory device regardless of the temperature of the memory device.

Abstract: A bandgap reference circuit includes a current generation circuit connected to a voltage generation circuit connected to a smart clamping circuit, and a discharge circuit connected to the current generation circuit and the voltage generation circuit. The discharge circuit initially discharges a potential in the current and voltage generation circuits to improve repeatability. A start circuit within the current generation circuit then initializes the reference output at about the supply voltage to improve the speed and settling time of the output signal. The current generation circuit sources a current to the voltage generation circuit that translates the current having a positive function of temperature +TC into a reference voltage. The smart clamping circuit further generates a clamping voltage having a negative function of temperature ?TC and a load resistance.

Abstract: Flash memory array systems and methods are disclosed for producing a regulated boosted word line voltage for read operations. The system comprises a multi-stage voltage boost circuit operable to receive a supply voltage and one or more output signals from a supply voltage detection circuit to generate the boosted word line voltage having a value greater than the supply voltage. The voltage boost circuit comprises a precharge circuit and a plurality of boost cells connected to a common node of the boosted word line, and a timing control circuit. The stages of the plurality of boost cells are coupled in series for charge sharing between the stages, and couple a predetermined number of boost cells to the boosted word line common node to provide an intermediate voltage to the boosted word line during the pre-boost timing, thereby anticipating a final boosted word line voltage provided during the boost timing.

Abstract: Flash memory array systems and methods are disclosed for producing a regulated boosted word line voltage for read operations. The system comprises a multi-stage voltage boost circuit operable to receive a supply voltage and one or more output signals from a supply voltage detection circuit to generate the boosted word line voltage having a value greater than the supply voltage. The voltage boost circuit comprises a precharge circuit and a plurality of boost cells connected to a common node of the boosted word line, and a timing control circuit. The stages of the plurality of boost cells are coupled in series for charge sharing between the stages, and couple a predetermined number of boost cells to the boosted word line common node to provide an intermediate voltage to the boosted word line during the pre-boost timing, thereby anticipating a final boosted word line voltage provided during the boost timing.

Abstract: A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.

Abstract: According to one exemplary embodiment, a buffer circuit is configured to receive a supply voltage and an input reference voltage, the buffer circuit has a first FET operating in saturation region where the source of the first FET is coupled to the output reference voltage. The first FET can be configured, for example, as an open-loop voltage follower and, by way of example, a first resistor can be used to couple the source of the first FET to the output reference voltage. A tracking circuit is connected to the buffer circuit. The tracking circuit comprises a second FET also operating in saturation region where the drain of the second FET is coupled to the output reference voltage. Both the first and second FETs can be, for example, depletion mode transistors.

Abstract: A memory circuit senses current in a target cell during a read operation. According to one exemplary embodiment, the memory circuit comprises the target cell, a first neighboring cell, and an operational amplifier. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a drain voltage. A sensing circuit is coupled at a first node to at least one of the first bit line or the second bit line. The first neighboring cell has a third bit line connected to a second node. The operational amplifier has an output terminal connected at the second node to the third bit line. The operational amplifier has a noninverting input terminal connected to said first node, and also has an inverting input terminal connected to the second node.

Abstract: The present invention is a method for fabricating nitride memory cells using a floating gate fabrication process. In one embodiment of the present invention, the fabrication process of a floating gate memory cell is accessed. The floating gate memory cell fabrication process is then altered to produce an altered floating gate memory cell fabrication process. The altered floating gate memory cell fabrication process is then used to form a nitride memory cell.

Abstract: A flash memory array having multiple dual bit memory cells divided into section attached to a wordline and a pair of reference cells logically associated with each section. A method of reprogramming a section or sections of words that are required to be changed includes inputting allowed changes to the flash memory array, reading word or words to be changed in each section, programming bits in word or words to be changed in each section, refreshing previously programmed bits in the word or words that are changed, refreshing previously programmed bits in the word or words changed in each section, refreshing previously programmed bits in the remaining word or words in each section and refreshing previously programmed in each pair of reference cells in the section in which changes have been made.

Abstract: A method of cycling dual bit flash memory arrays having a plurality of dual bit flash memory cells arranged in a plurality of sectors with each sector having an associated reference array that have dual bit flash memory cells that are cycled with the plurality of dual bit flash memory cells in the sectors. The dual bit flash memory cells in the associated reference array are then programmed.

Abstract: A method of erasing a sector of flash memory cells wherein a first set of preset pre-erase voltages is applied to the sector of flash memory cells. After the first set of preset pre-erase voltages is applied it is determined if another set of preset pre-erase voltages is to be applied to the sector of flash memory cells. If another set of preset pre-erase voltages is applied and if another set of preset pre-erase set of pre-erase voltages is not to be applied, a standard erase routine is applied to the sector.

Abstract: A method for providing a modified threshold voltage distribution for a dynamic reference array in a flash memory cell array. The dynamic reference array and an associated core memory cell array are programmed using two different programming processes to produce different Vt distributions for the dynamic reference array and the core memory cell array. The dynamic reference array is programmed using a finer program pulse to achieve a smaller distribution width, thus enhancing the read margin for the memory cell array. The finer pulse may be of shorter duration or of smaller amplitude. The finer programming process may be applied to one or more threshold voltage distributions (states) in the memory cell array.

Abstract: A flash memory array having multiple dual bit memory cells divided into section attached to a wordline and a pair of reference cells logically associated with each section. A method of reprogramming a section or sections of words that are required to be changed includes inputting allowed changes to the flash memory array, reading word or words to be changed in each section, programming bits in word or words to be changed in each section, refreshing previously programmed bits in the word or words that are changed, refreshing previously programmed bits in the word or words changed in each section, refreshing previously programmed bits in the remaining word or words in each section and refreshing previously programmed in each pair of reference cells in the section in which changes have been made.

Abstract: Method and apparatus for a memory circuit having a sense amplifier circuit having a sensing amplifier connected to read the data content output of a memory cell where the sense amplifier circuit includes a current source transistor having a gate terminal and having a drain terminal connected to a voltage supply and having a source terminal connected to the sensing amplifier, with a selectable source current in order to account for variation from a desired source current due to variations in the designed source current transistor performance parameters.

Abstract: A voltage control circuit that programs or erases memory cells comprises an internal voltage value store, a register device selectively coupled to an external voltage value source or the internal voltage value store to receive a voltage value, a voltage output circuit coupled to the register device to receive the voltage value and to output a corresponding voltage to the memory cells, and a verify circuit determining the time to successfully program or erase the memory cells. The register device allows the memory cells to be programmed or erased with voltage values designated by the external voltage value source to determine programming and erasing characteristics of the memory cells. Voltage values producing acceptable programming and erasing characteristics are saved in the internal voltage value store.