Abstract: A method includes forming a stack of multi-layers, each multi-layer including a first isolation layer, a semiconductor layer, and a first metal layer; etching the stack of multi-layers to form gate trenches in a channel region; removing the first isolation layers and the first metal layers from the channel region, resulting in channel portions of the semiconductor layers exposed in the gate trenches; laterally recessing the first metal layers from the gate trenches, resulting in gaps between adjacent layers of the first isolation layers and the semiconductor layers; forming an inner spacer layer in the gaps; forming a ferroelectric (FE) layer surrounding each of the channel portions and over sidewalls of the gate trenches, wherein the inner spacer layer is disposed laterally between the FE layer and the first metal layers; and depositing a metal gate layer over the FE layer and filling the gate trenches.

Abstract: A device includes a substrate, gate stacks, source/drain (S/D) features over the substrate, S/D contacts over the S/D features, and one or more dielectric layers over the gate stacks and the S/D contacts. A via structure penetrates the one or more dielectric layers and electrically contacts one of the gate stacks and the S/D contacts. And a ferroelectric (FE) stack is over the via structure and directly contacting the via structure, wherein the FE stack includes an FE feature and a top electrode over the FE feature.

Abstract: Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.

Abstract: A semiconductor memory structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes spacers formed over opposite sides of the gate structure. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure beside the spacers. The gate structure includes a III-V ferroelectric layer formed between an interfacial layer and a gate electrode layer.

Abstract: A semiconductor device is provided. The device includes a first pair and a second pair of source/drain features over a semiconductor substrate. The first pair of source/drain features are p-type doped. The second pair of source/drain features are n-type doped. A first stack of semiconductor layers connect the first pair of source/drain features along a first direction. A second stack of semiconductor layers connect the second pair of source/drain features along a second direction. A first gate is between vertically adjacent layers of the first stack of semiconductor layers. The first gate has a first portion that has a first dimension along the first direction. A second gate is between vertically adjacent layers of the second stack of semiconductor layers. The second gate has a second portion that has a second dimension along the second direction. The second dimension is larger than the first dimension.

Abstract: A memory circuit includes a memory array and a control circuit. A first column of the memory array includes a select line, first and second bit lines, a first subset of memory cells coupled to the select line and the first bit line, and a second subset of memory cells coupled to the select line and the second bit line. The control circuit is configured to simultaneously activate each of the select line and the first bit line and, during a period in which the select line and first bit line are simultaneously activated, activate a first plurality of word lines, each word line of the first plurality of word lines being coupled to a memory cell of the first subset of memory cells.

Abstract: A semiconductor device is provided. The device includes a first pair and a second pair of source/drain features over a semiconductor substrate. The first pair of source/drain features are p-type doped. The second pair of source/drain features are n-type doped. A first stack of semiconductor layers connect the first pair of source/drain features along a first direction. A second stack of semiconductor layers connect the second pair of source/drain features along a second direction. A first gate is between vertically adjacent layers of the first stack of semiconductor layers. The first gate has a first portion that has a first dimension along the first direction. A second gate is between vertically adjacent layers of the second stack of semiconductor layers. The second gate has a second portion that has a second dimension along the second direction. The second dimension is larger than the first dimension.

Abstract: An array substrate and a display device are provided. The array substrate includes sub-pixels arranged in a first direction and a second direction, gate lines extending in the first direction and data lines extending in the second direction. The data lines include a first data line and a second data line alternately arranged, the first data line and the second data line are respectively configured to transmit voltages of different polarities, and different sub-pixels connected to a same data line are connected to different gate lines. Two adjacent sub-pixels arranged in the first direction are respectively connected to the first data line and the second data line, and one column of sub-pixels extending in the second direction are connected to the first data line, or one column of sub-pixels extending in the second direction are connected to the second data line.

Abstract: A driving circuit for a display panel, a display panel, and a display device are provided. The driving circuit includes a plurality of driving units, wherein at least one of the driving units includes M dummy pins, at least one of the M dummy pins is configured to be electrically connected to at least one clock pin of the display panel, and M is an integer greater than or equal to 1.

Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first negative capacitance material over a substrate and patterning the first negative capacitance material to form a fin structure over the substrate. The method also includes forming a source feature and a drain feature in and protruding from a source region and a drain region of the fin structure. The method also includes forming a gate dielectric structure between the source feature and the drain feature to cover a channel region of the fin structure and forming a gate electrode layer over the gate dielectric structure.

Abstract: The present disclosure provides fingerprint recognition substrate including fingerprint recognition units arranged in array, signal reading line groups and gating circuits, fingerprint recognition units are divided into first fingerprint recognition groups arranged along row direction, first fingerprint recognition groups, signal reading line groups and gating circuits are in one-to-one correspondence with one another; first fingerprint recognition group includes fingerprint recognition units consecutively arranged in row direction, signal reading line group includes signal reading lines each coupled to corresponding column of fingerprint recognition units; gating circuit includes switch circuits each coupled to one signal transmission channel on signal receiving unit through corresponding switch circuit; among all signal reading lines, different signal reading lines in same signal reading line group are coupled to different signal transmission channels, and at least two signal reading lines in different sign

Abstract: Provided is an array substrate. The array substrate includes: a base substrate, and a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels and a plurality of touch signal lines disposed on the base substrate. The data lines have a plurality of first extending parts and a plurality of second extending parts which are in an alternating arrangement. When the array substrate is used to prepare a liquid crystal display panel and the liquid crystal display panel is displaying, in each column of the sub-pixels, the voltage polarities of the two adjacent sub-pixels which respectively belong to two adjacent first pixel regions are opposite.

Abstract: The fingerprint recognition panel includes fingerprint recognition circuits arranged in a matrix, reading signal lines, a gate driving circuit and scanning lines connected with the gate driving circuit. The gate driving circuit is for outputting scanning signals to the scanning lines successively; each fingerprint recognition circuit is in connection with two scanning lines, a reading control end is connected with a first scanning line, and a reset control end is connected with a second scanning line; the first scanning line in connection with the fingerprint recognition circuits of the nth row and the second scanning line in connection with the fingerprint recognition circuits of the (n?m)th row are the same; or the second scanning line in connection with the fingerprint recognition circuits of the nth row and the first scanning line in connection with the fingerprint recognition circuits of the (n?m)th row are the same.

Abstract: The present disclosure provides a display substrate, a method for driving same, and a display device, which belong to the field of display technologies. In the display substrate, in a plurality of pixels connected to each shift circuit, the respective pixels sharing the same data line have the same color, and each shift circuit is connected to one turn-on signal terminal. Through flexible control over a turn-on signal provided by the turn-on signal terminal, each data line can continuously provide data signals to the pixels of the same color. In this way, when a pure-color picture is displayed, the number of times of potential reversal on each data line is less, which effectively reduces power consumption of the display device.

Abstract: A fingerprint detection control circuit, a fingerprint detection control method and a display device. The fingerprint detection control circuit includes a sensing circuitry, a resetting circuitry, a control circuitry and a conversion circuitry. The control circuitry provides a switch control signal to a control end of the resetting circuitry under the control of a first control signal. The resetting circuitry provides a resetting voltage to a conversion control end under the control of a potential at its control end. The conversion circuitry converts a photovoltage signal into a corresponding current signal under the control of a potential at the conversion control end when a first voltage end is electrically connected to a first signal output end, and outputs the current signal via the first signal output end.

Abstract: The present disclosure provides a semiconductor structure, including a first layer including a logic device, a second layer over the first layer including a first type memory device, and a though silicon via (TSV) electrically connecting the logic device and the first type memory device.

Abstract: A device includes a first channel; a second channel above the first channel; and a gate structure surrounding the first and second channels, wherein the gate structure includes a ferroelectric (FE) layer surrounding the first and second channels and a gate metal layer surrounding the FE layer. The device further includes two first electrodes connected to two sides of the first channel; two second electrodes connected to two sides of the second channel; a dielectric layer between the first and the second electrodes; and an inner spacer layer between the two first electrodes and the gate structure.

Abstract: A memory device includes a bit line, a source line, a plurality of word lines, and a memory cell. The memory cell includes a plurality of memory strings coupled in parallel between the bit line and the source line. Each of the plurality of memory strings includes a plurality of memory elements coupled in series between the bit line and the source line, and electrically coupled correspondingly to the plurality of word lines.

Abstract: A semiconductor device includes a substrate, a fin protruding over the substrate, a gate structure over the fin, a bottom electrode over and electrically coupled to the gate structure, a ferroelectric layer around the bottom electrode, and a top electrode around the ferroelectric layer.