Abstract: In an embodiment, a method includes forming a multi-layer stack including alternating layers of an isolation material and a semiconductor material, patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, where the first channel structure includes the semiconductor material, depositing a memory film layer over the first channel structure, etching a first trench extending through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, where the first dummy bit line and first dummy source line each include the semiconductor material, and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.

Abstract: Fin-like field effect transistors (FinFETs) and methods of fabrication thereof are disclosed herein. The FinFETs disclosed herein have gate air spacers integrated into their gate structures. An exemplary transistor includes a fin and a gate structure disposed over the fin between a first epitaxial source/drain feature and a second epitaxial source/drain feature. The gate structure includes a gate electrode, a gate dielectric, and gate air spacers disposed between the gate dielectric and sidewalls of the gate electrode.

Abstract: A method of forming a semiconductor device includes: forming a first fin protruding above a substrate; forming first source/drain regions over the first fin; forming a first plurality of nanostructures over the first fin between the first source/drain regions; forming a first gate structure around the first plurality of nanostructures; and forming a first ferroelectric capacitor over and electrically coupled to the first gate structure.

Abstract: An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.

Abstract: The present disclosure discloses an array substrate, a liquid crystal display panel, and a display apparatus, which relate to the field of display technologies. The array substrate includes a first base and a plurality of photosensitive devices disposed on the first base. The photosensitive device can recognize fingerprints. In this way, the screen-to-body ratio of a display apparatus manufactured by using the array substrate is effectively increased. When an orthographic projection of the photosensitive device in the array substrate onto the first base at least partially overlaps with a white sub-pixel region, a pixel aperture ratio of the array substrate can be increased, so that a display apparatus that is subsequently manufactured by using the array substrate has a relatively good display effect.

Abstract: A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad.

Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer, a ferroelectric layer and oxygen scavenging layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. The oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.

Abstract: A display device is disclosed. The display device includes an array substrate and at least two driving units. The array substrate includes a peripheral region and a display region, the array substrate further includes a peripheral grounding line and a test line, wherein the peripheral grounding line is located in the peripheral region, and the test line is located in the peripheral region. The at least two driving units are located on at least one side of the array substrate, the driving unit includes at least two grounding pins, a grounding pin of at least one of the driving units is connected to the peripheral grounding line, and each of at least one grounding pin of one of two adjacent driving units is electrically connected to a corresponding grounding pin of the other adjacent driving unit.

Abstract: A smoothly adjustable artboard comprises: a base configured for fixing, an adjusting bracket configured to adjust the height and angle of the artboard, and a painting plate configured to place drawing paper, and the adjusting bracket is arranged between the base and the painting plate, wherein the adjusting bracket includes a connecting seat, a connecting bracket, a force applying mechanism, a cam member, a roller and a one-way limiting mechanism, the roller is rotatably arranged on the connecting bracket and is located at one end close to the base, and one end of the force applying mechanism is connected with the connecting seat, and the other end of the force applying mechanism is connected with the cam member, wherein a curved surface of the cam member is configured to press against the roller under the pushing action of the force applying mechanism.

Abstract: A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.

Abstract: Embodiments provide an integrated capacitor disposed directly over and aligned to a vertical gate all around memory cell transistor. In some embodiments, an air gap may be provided between adjacent word lines to provide a low k dielectric effect between word lines. In some embodiments, a bottom bitline structure may be split across multiple layers. In some embodiments, a second tier of vertical cells may be positioned over a first tier of vertical cells.

Abstract: The present disclosure provides a power module assembly and a converter. The power module assembly includes a power module and a capacitor module, and the power module and the capacitor module are configured to be detachably connected; the power module includes a first bus bar, and the first bus bar includes a first connection portion and a power installation portion connected to the first connection portion; the capacitor module includes a second bus bar, and the second bus bar includes a second connection portion and a capacitor installation portion connected to the second connection portion, wherein the first connection portion and the second connection portion extend along a first direction, and the power installation portion and the capacitor installation portion extend along a second direction; the first connection portion and the second connection portion are connected by a fastener.

Abstract: A semiconductor device includes a semiconductor substrate, first and second stack units disposed over the semiconductor substrate, and a feature disposed between the first and second stack units. Each of the first and second stack units includes at least one stack that includes a conductive film and a dielectric film stacked on each other. The feature includes a plurality of repeating units and a plurality of separators disposed to alternate with the repeating units. Each of the repeating units includes an inner portion including a pair of conductive pillars, and an outer portion including a memory film and a channel film. A method for manufacturing the semiconductor device is also disclosed.

Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The gate stack is partially embedded in the first nanostructure. The semiconductor device structure includes a first source/drain layer surrounding the first nanostructure and adjacent to the gate stack. The semiconductor device structure includes a contact structure surrounding the first source/drain layer. A first portion of the contact structure is between the first source/drain layer and the substrate.

Abstract: A memory device includes a multi-layer stack, a plurality of channel layers and a plurality of ferroelectric layers. The multi-layer stack is disposed on a substrate and includes a plurality of gate layers and a plurality of dielectric layers stacked alternately. The plurality of channel layers penetrate through the multi-layer stack and are laterally spaced apart from each other, wherein the plurality of channel layers include a first channel layer and a second channel layer, and a first electron mobility of the first channel layer is different from a second electron mobility of the second channel layer. Each of the plurality of channel layers are spaced apart from the multi-layer stack by one of the plurality of ferroelectric layers, respectively.

Abstract: A display substrate includes: a base substrate (100); a plurality of sub-pixels (R, G, B) located on the base substrate (100), every two rows of sub-pixels (R, G, B) constituting a pixel group; a plurality of first gate lines (Gate1) located at first row gaps between the pixel groups, two first gate lines (Gate1) being arranged at each first row gap; and a plurality of photosensors (101), the orthographic projection of each row of photosensors (101) on the base substrate (100) completely covering a second row gap in the pixel group and partially overlapping with the orthographic projections of the sub-pixels (R, G, B), thereby avoiding the bright and dark difference between adjacent rows and ensuring the aperture ratio.

Abstract: A display device is disclosed. The display device includes an array substrate and at least two driving units. The array substrate includes a peripheral region and a display region, the peripheral region surrounds the display region, the array substrate further includes a peripheral grounding line, and the peripheral grounding line is located in the peripheral region and surrounds the display region. The at least two driving units are located on at least one side of the array substrate, the driving unit includes at least two grounding pins, a grounding pin of at least one of the driving units is connected to the peripheral grounding line, and each of at least one grounding pin of one of two adjacent driving units is electrically connected to a corresponding grounding pin of the other adjacent driving unit.

Abstract: An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.