Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.

Abstract: A light emission apparatus includes a laser diode configured to emit a light; a laser driver electrically coupled to the laser diode, the laser driver being configured to drive the laser diode to generate the light; and an optical module arranged to receive the light emitted by the laser diode, the optical module comprising at least one optical element and being configured to adjust the light and emits a transmitting light; wherein the transmitting light emits from the optical module with an illumination angle and the optical module adjusts the light to vary the illumination angle.

Abstract: A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

Abstract: A light-emitting device comprises a substrate; a first light-emitting unit and a second light-emitting unit formed on the substrate, each of the first light-emitting unit and the second light-emitting unit comprises a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the first light-emitting unit comprises a first semiconductor mesa and a first surrounding part surrounding the first semiconductor mesa, and the second light-emitting unit comprises a second semiconductor mesa and a second surrounding part surrounding the second semiconductor mesa; a trench formed between the first light-emitting unit and the second light-emitting unit and exposing the substrate; a first insulating layer comprising a first opening on the first surrounding part and a second opening on the second semiconductor layer of the second light-emitting unit; and a connecting electrode comprising a first connecting part on the first

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A semiconductor device includes a first electrode, a first dielectric layer, a second electrode and an insulating layer. The first dielectric layer is disposed on the first electrode. The second electrode is disposed in the first dielectric layer. The insulating layer is disposed in the first dielectric layer and between the second electrode and the first electrode and between the second electrode and the first dielectric layer. The first electrode and the second electrode are electrically isolated by the insulating layer.

Abstract: A method for manufacturing a semiconductor device includes the following steps. A transition metal layer is formed over a substrate in a reaction chamber; a chalcogen-containing fluid is flowed into the reaction chamber; and a heating process is performed in the reaction chamber over the transition metal layer with the chalcogen-containing fluid to transform the transition metal layer into a two-dimensional (2D) material layer over the substrate.

Abstract: A device includes a substrate; a first layer over the substrate, the first layer containing a plurality of fin features and a trench between two adjacent fin features. The device also includes a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

Abstract: The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

Abstract: A device includes a substrate; a first layer over the substrate, the first layer containing a plurality of fin features and a trench between two adjacent fin features. The device also includes a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

Abstract: The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

Abstract: A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

Abstract: A semiconductor structure includes a substrate and an interconnect. The substrate has a semiconductor device. The interconnect is disposed over the substrate and electrically coupled to the semiconductor device, and includes a metallization layer and a capping layer. The metallization layer is disposed over the substrate and includes a via portion and a line portion connecting to the via portion. The capping layer covers the line portion, where the line portion is sandwiched between the via portion and the capping layer, and the capping layer includes a plurality of sub-layers.

Abstract: A device includes a substrate, a dielectric layer over the substrate, and a conductive interconnect in the dielectric layer. The conductive interconnect includes a barrier/adhesion layer and a conductive layer over the barrier/adhesion layer. The barrier/adhesion layer includes a material having a chemical formula MXn, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2.

Abstract: Provided is an interconnect structure including: a first conductive feature, disposed in a first dielectric layer; a second conductive feature, disposed over the first conductive feature and the first dielectric layer; a via, disposed between the first and second conductive features and being in direct contact with the first and second conductive features; and a barrier structure, lining a sidewall and a portion of a bottom surface of the second conductive feature, a sidewall of the via, a portion of a top surface of the first conductive feature, and a top surface of the first dielectric layer.

Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

Abstract: Provided is a method of forming an interconnect structure including: forming a via; forming a first barrier layer to at least cover a top surface and a sidewall of the via; forming a first dielectric layer on the first barrier layer; performing a planarization process to remove a portion of the first dielectric layer and a portion of the first barrier layer, thereby exposing the top surface of the via; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has an opening exposing the top surface of the via; forming a blocking layer on the top surface of the via; forming a second barrier layer on the second dielectric layer; removing the blocking layer to expose the top surface of the via; and forming a conductive feature in the opening, wherein the conductive feature is in contact with the top surface of the via.

Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

Abstract: Provided is a method of forming an interconnect structure including: forming a via; forming a first barrier layer to at least cover a top surface and a sidewall of the via; forming a first dielectric layer on the first barrier layer; performing a planarization process to remove a portion of the first dielectric layer and a portion of the first barrier layer, thereby exposing the top surface of the via; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has an opening exposing the top surface of the via; forming a blocking layer on the top surface of the via; forming a second barrier layer on the second dielectric layer; removing the blocking layer to expose the top surface of the via; and forming a conductive feature in the opening, wherein the conductive feature is in contact with the top surface of the via.

Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.