Abstract: A device includes a substrate, a dielectric layer over the substrate, and a conductive interconnect in the dielectric layer. The conductive interconnect includes a barrier/adhesion layer and a conductive layer over the barrier/adhesion layer. The barrier/adhesion layer includes a material having a chemical formula MXn, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2.

Abstract: A semiconductor device including a substrate, a semiconductor layer, a gate, a dielectric structure, and a source/drain structure is provided. The semiconductor layer is disposed on the substrate, and is made of a first low dimensional material. The gate is disposed on the substrate and overlaps the semiconductor layer. The dielectric structure is disposed on the semiconductor layer and includes a trench structure reaching a portion of the semiconductor layer. The source/drain structure includes a barrier layer made of a second low dimensional material continuously extending along the trench structure and a metal fill filling a volume surrounded by the barrier layer.

Abstract: A method of forming a semiconductor device is provided. A first ferroelectric inducing layer including Ru is deposited on a substrate. A ferroelectric layer including HfZrO is deposited on the first ferroelectric inducing layer. A second ferroelectric inducing layer including Ru is deposited on the ferroelectric layer, wherein the HfZrO of the ferroelectric layer is in physical contact with the Ru of the first ferroelectric inducing layer and the Ru of the second ferroelectric inducing layer. The second ferroelectric inducing layer, the ferroelectric layer and the first ferroelectric inducing layer are patterned.

Abstract: A method of forming a semiconductor device comprises the following steps. A dielectric layer is formed over a substrate. A 2D material layer is formed over the dielectric layer. An adhesion layer is formed over the 2D material layer. Source/drain electrodes are formed on opposite sides of the adhesion layer. A first high-k gate dielectric layer is formed over the adhesion layer, wherein the adhesion layer has a material different from a material of the first high-k gate dielectric layer.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a channel layer, an adhesion layer disposed over the channel layer, a first hafnium-containing dielectric layer disposed over the adhesion layer, a second hafnium-containing dielectric layer disposed over the first hafnium-containing dielectric layer, a gate structure, and source and drain terminals. The second hafnium-containing dielectric layer has a hafnium content lower than a hafnium content of the first hafnium-containing dielectric layer. A dielectric constant of the second hafnium-containing dielectric layer is larger than a dielectric constant of the first hafnium-containing dielectric layer.

Abstract: A device includes a substrate, a dielectric layer over the substrate, and a conductive interconnect in the dielectric layer. The conductive interconnect includes a barrier/adhesion layer and a conductive layer over the barrier/adhesion layer. The barrier/adhesion layer includes a material having a chemical formula MXn, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2.

Abstract: Provided is an interconnect structure including: a first conductive feature, disposed in a first dielectric layer; a second conductive feature, disposed over the first conductive feature and the first dielectric layer; a via, disposed between the first and second conductive features and being in direct contact with the first and second conductive features; and a barrier structure, lining a sidewall and a portion of a bottom surface of the second conductive feature, a sidewall of the via, a portion of a top surface of the first conductive feature, and a top surface of the first dielectric layer.

Abstract: Provided is an interconnect structure including: a first conductive feature, disposed in a first dielectric layer; a second conductive feature, disposed over the first conductive feature and the first dielectric layer; a via, disposed between the first and second conductive features and being in direct contact with the first and second conductive features; and a barrier structure, lining a sidewall and a portion of a bottom surface of the second conductive feature, a sidewall of the via, a portion of a top surface of the first conductive feature, and a top surface of the first dielectric layer.

Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

Abstract: A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: A device includes a substrate; a first layer over the substrate, the first layer containing a plurality of fin features and a trench between two adjacent fin features. The device also includes a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

Abstract: A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A semiconductor device includes a first electrode, a first dielectric layer, a second electrode and an insulating layer. The first dielectric layer is disposed on the first electrode. The second electrode is disposed in the first dielectric layer. The insulating layer is disposed in the first dielectric layer and between the second electrode and the first electrode and between the second electrode and the first dielectric layer. The first electrode and the second electrode are electrically isolated by the insulating layer.

Abstract: A method for manufacturing a semiconductor device includes the following steps. A transition metal layer is formed over a substrate in a reaction chamber; a chalcogen-containing fluid is flowed into the reaction chamber; and a heating process is performed in the reaction chamber over the transition metal layer with the chalcogen-containing fluid to transform the transition metal layer into a two-dimensional (2D) material layer over the substrate.

Abstract: A device includes a substrate; a first layer over the substrate, the first layer containing a plurality of fin features and a trench between two adjacent fin features. The device also includes a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

Abstract: The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

Abstract: A device includes a substrate; a first layer over the substrate, the first layer containing a plurality of fin features and a trench between two adjacent fin features. The device also includes a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.