Abstract: A pipe latch circuit may include first and second latching circuit groups. The first latching circuit group may control a latching operation and an output operation based on a plurality of pipe input control signals. The second latching circuit group may control a latching operation and an output operation based on the plurality of pipe input control signals and a plurality of pipe output control signals.

Abstract: A pipe latch circuit may include first and second latching circuit groups. The first latching circuit group may control a latching operation and an output operation based on a plurality of pipe input control signals. The second latching circuit group may control a latching operation and an output operation based on the plurality of pipe input control signals and a plurality of pipe output control signals.

Abstract: A pipe latch circuit may include first and second latching circuit groups. The first latching circuit group may control a latching operation and an output operation based on a plurality of pipe input control signals. The second latching circuit group may control a latching operation and an output operation based on the plurality of pipe input control signals and a plurality of pipe output control signals.

Abstract: A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.

Abstract: A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.

Abstract: A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.

Abstract: A test mode circuit of a semiconductor device includes a test mode activating signal generation unit suitable for generating a test mode activating signal in response to a test signal; a test clock generation unit suitable for generating a plurality of test clocks in response to the test mode activating signal and a control clock; a test control signal generation unit suitable for generating test control signals based on the plurality of test clocks of a control signal input cycle, wherein the plurality of test clocks have the control signal input cycle and a data input cycle; and an internal control signal generation unit suitable for generating a plurality of control signals to perform a test operation in response to the test control signals and input data.

Abstract: A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.

Abstract: A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels.

Abstract: The stack package includes: a plurality of chips each stacked with a plurality of layers; and a plurality of pads respectively formed on the plurality of chips. Each chip includes: a ground path unit configured to form a current path between a pad and a ground stage; a selection unit configured to selectively control a connection path electrically coupled to the pad according to a chip enable signal; and a controller configured to selectively control a connection between the selection unit and the ground path unit according to a control signal.

Abstract: A semiconductor memory device includes a memory cell unit including a plurality of memory banks each including a pair of a first memory bank and a second memory bank, a sense amplifier group including a plurality of sense amplifier units each including a first sense amplifier and a second sense amplifier coupled to the first memory bank and the second memory bank, respectively, and a control logic block generating a first column selection signal to transfer data of the first memory bank to the first sense amplifier and a second column selection signal to transfer data of the second memory bank to the second sense amplifier, wherein an active section of the first column selection signal overlaps an active section of the second column selection signal.

Abstract: A test mode circuit of a semiconductor device includes a test mode activating signal generation unit suitable for generating a test mode activating signal in response to a test signal; a test clock generation unit suitable for generating a plurality of test clocks in response to the test mode activating signal and a control clock; a test control signal generation unit suitable for generating test control signals based on the plurality of test clocks of a control signal input cycle, wherein the plurality of test clocks have the control signal input cycle and a data input cycle; and an internal control signal generation unit suitable for generating a plurality of control signals to perform a test operation in response to the test control signals and input data.

Abstract: A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels.

Abstract: A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels.

Abstract: The stack package includes: a plurality of chips each stacked with a plurality of layers; and a plurality of pads respectively formed on the plurality of chips. Each chip includes: a ground path unit configured to form a current path between a pad and a ground stage; a selection unit configured to selectively control a connection path electrically coupled to the pad according to a chip enable signal; and a controller configured to selectively control a connection between the selection unit and the ground path unit according to a control signal.

Abstract: A memory device includes a first main page buffer array configured to access data of a first main memory array; a second main page buffer array configured to access data of a second main memory array; a redundancy page buffer array configured to access data of a redundancy memory array replacing the first and second main memory array; a first redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside of the memory device through a first redundancy bus, when a first column address indicates one or more defective columns of the first main memory array; and a second redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside through a second redundancy bus, when a second column address indicates one or more defective columns of the second main memory array.

Abstract: A semiconductor memory device includes a memory cell unit including a plurality of memory banks each including a pair of a first memory bank and a second memory bank, a sense amplifier group including a plurality of sense amplifier units each including a first sense amplifier and a second sense amplifier coupled to the first memory bank and the second memory bank, respectively, and a control logic block generating a first column selection signal to transfer data of the first memory bank to the first sense amplifier and a second column selection signal to transfer data of the second memory bank to the second sense amplifier, wherein an active section of the first column selection signal overlaps an active section of the second column selection signal.

Abstract: A control method of a multi-chip package memory device includes the steps of applying stack signals to stack pads of memory dies, applying a repair signal to repair pads of the respective memory dies, setting one or more repaired memory dies for replacing a failed memory die among the memory dies, based on the repair signal applied to the respective memory dies, and setting stack states indicating a logical access order of the other memory dies excluding the repaired memory die, based on the stack signals applied to the other memory dies.

Abstract: A control method of a multi-chip package memory device includes the steps of applying stack signals to stack pads of memory dies, applying a repair signal to repair pads of the respective memory dies, setting one or more repaired memory dies for replacing a failed memory die among the memory dies, based on the repair signal applied to the respective memory dies, and setting stack states indicating a logical access order of the other memory dies excluding the repaired memory die, based on the stack signals applied to the other memory dies.

Abstract: A memory device includes a first main page buffer array configured to access data of a first main memory array; a second main page buffer array configured to access data of a second main memory array; a redundancy page buffer array configured to access data of a redundancy memory array replacing the first and second main memory array; a first redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside of the memory device through a first redundancy bus, when a first column address indicates one or more defective columns of the first main memory array; and a second redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside through a second redundancy bus, when a second column address indicates one or more defective columns of the second main memory array.