Patents by Inventor Bo-Kyeom Kim

Bo-Kyeom Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10186314
    Abstract: A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: January 22, 2019
    Assignee: SK Hynix Inc.
    Inventor: Bo-Kyeom Kim
  • Publication number: 20180130523
    Abstract: A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.
    Type: Application
    Filed: January 3, 2018
    Publication date: May 10, 2018
    Inventor: Bo-Kyeom KIM
  • Patent number: 9953700
    Abstract: A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 24, 2018
    Assignee: SK Hynix Inc.
    Inventor: Bo-Kyeom Kim
  • Patent number: 9817065
    Abstract: A test mode circuit of a semiconductor device includes a test mode activating signal generation unit suitable for generating a test mode activating signal in response to a test signal; a test clock generation unit suitable for generating a plurality of test clocks in response to the test mode activating signal and a control clock; a test control signal generation unit suitable for generating test control signals based on the plurality of test clocks of a control signal input cycle, wherein the plurality of test clocks have the control signal input cycle and a data input cycle; and an internal control signal generation unit suitable for generating a plurality of control signals to perform a test operation in response to the test control signals and input data.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: November 14, 2017
    Assignee: SK Hynix Inc.
    Inventors: Bo Kyeom Kim, Tae Seung Shin
  • Publication number: 20170323678
    Abstract: A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.
    Type: Application
    Filed: September 29, 2016
    Publication date: November 9, 2017
    Inventor: Bo-Kyeom KIM
  • Patent number: 9558829
    Abstract: A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: January 31, 2017
    Assignee: SK HYNIX INC.
    Inventor: Bo Kyeom Kim
  • Patent number: 9443826
    Abstract: The stack package includes: a plurality of chips each stacked with a plurality of layers; and a plurality of pads respectively formed on the plurality of chips. Each chip includes: a ground path unit configured to form a current path between a pad and a ground stage; a selection unit configured to selectively control a connection path electrically coupled to the pad according to a chip enable signal; and a controller configured to selectively control a connection between the selection unit and the ground path unit according to a control signal.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: September 13, 2016
    Assignee: SK hynix Inc.
    Inventors: Tae Hyun Kim, Bo Kyeom Kim
  • Patent number: 9424941
    Abstract: A semiconductor memory device includes a memory cell unit including a plurality of memory banks each including a pair of a first memory bank and a second memory bank, a sense amplifier group including a plurality of sense amplifier units each including a first sense amplifier and a second sense amplifier coupled to the first memory bank and the second memory bank, respectively, and a control logic block generating a first column selection signal to transfer data of the first memory bank to the first sense amplifier and a second column selection signal to transfer data of the second memory bank to the second sense amplifier, wherein an active section of the first column selection signal overlaps an active section of the second column selection signal.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: August 23, 2016
    Assignee: SK Hynix Inc.
    Inventor: Bo Kyeom Kim
  • Publication number: 20160216325
    Abstract: A test mode circuit of a semiconductor device includes a test mode activating signal generation unit suitable for generating a test mode activating signal in response to a test signal; a test clock generation unit suitable for generating a plurality of test clocks in response to the test mode activating signal and a control clock; a test control signal generation unit suitable for generating test control signals based on the plurality of test clocks of a control signal input cycle, wherein the plurality of test clocks have the control signal input cycle and a data input cycle; and an internal control signal generation unit suitable for generating a plurality of control signals to perform a test operation in response to the test control signals and input data.
    Type: Application
    Filed: June 12, 2015
    Publication date: July 28, 2016
    Inventors: Bo Kyeom KIM, Tae Seung SHIN
  • Publication number: 20160086667
    Abstract: A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels.
    Type: Application
    Filed: December 2, 2015
    Publication date: March 24, 2016
    Inventor: Bo Kyeom KIM
  • Patent number: 9230668
    Abstract: A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: January 5, 2016
    Assignee: SK Hynix Inc.
    Inventor: Bo Kyeom Kim
  • Publication number: 20150348941
    Abstract: The stack package includes: a plurality of chips each stacked with a plurality of layers; and a plurality of pads respectively formed on the plurality of chips. Each chip includes: a ground path unit configured to form a current path between a pad and a ground stage; a selection unit configured to selectively control a connection path electrically coupled to the pad according to a chip enable signal; and a controller configured to selectively control a connection between the selection unit and the ground path unit according to a control signal.
    Type: Application
    Filed: August 15, 2014
    Publication date: December 3, 2015
    Inventors: Tae Hyun KIM, Bo Kyeom KIM
  • Patent number: 9190176
    Abstract: A memory device includes a first main page buffer array configured to access data of a first main memory array; a second main page buffer array configured to access data of a second main memory array; a redundancy page buffer array configured to access data of a redundancy memory array replacing the first and second main memory array; a first redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside of the memory device through a first redundancy bus, when a first column address indicates one or more defective columns of the first main memory array; and a second redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside through a second redundancy bus, when a second column address indicates one or more defective columns of the second main memory array.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: November 17, 2015
    Assignee: SK Hynix Inc.
    Inventor: Bo-Kyeom Kim
  • Publication number: 20150200015
    Abstract: A semiconductor memory device includes a memory cell unit including a plurality of memory banks each including a pair of a first memory bank and a second memory bank, a sense amplifier group including a plurality of sense amplifier units each including a first sense amplifier and a second sense amplifier coupled to the first memory bank and the second memory bank, respectively, and a control logic block generating a first column selection signal to transfer data of the first memory bank to the first sense amplifier and a second column selection signal to transfer data of the second memory bank to the second sense amplifier, wherein an active section of the first column selection signal overlaps an active section of the second column selection signal.
    Type: Application
    Filed: June 9, 2014
    Publication date: July 16, 2015
    Inventor: Bo Kyeom KIM
  • Patent number: 8883521
    Abstract: A control method of a multi-chip package memory device includes the steps of applying stack signals to stack pads of memory dies, applying a repair signal to repair pads of the respective memory dies, setting one or more repaired memory dies for replacing a failed memory die among the memory dies, based on the repair signal applied to the respective memory dies, and setting stack states indicating a logical access order of the other memory dies excluding the repaired memory die, based on the stack signals applied to the other memory dies.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: November 11, 2014
    Assignee: SK Hynix Inc.
    Inventor: Bo Kyeom Kim
  • Publication number: 20140011300
    Abstract: A control method of a multi-chip package memory device includes the steps of applying stack signals to stack pads of memory dies, applying a repair signal to repair pads of the respective memory dies, setting one or more repaired memory dies for replacing a failed memory die among the memory dies, based on the repair signal applied to the respective memory dies, and setting stack states indicating a logical access order of the other memory dies excluding the repaired memory die, based on the stack signals applied to the other memory dies.
    Type: Application
    Filed: December 11, 2012
    Publication date: January 9, 2014
    Applicant: SK HYNIX INC.
    Inventor: Bo Kyeom KIM
  • Publication number: 20130315013
    Abstract: A memory device includes a first main page buffer array configured to access data of a first main memory array; a second main page buffer array configured to access data of a second main memory array; a redundancy page buffer array configured to access data of a redundancy memory array replacing the first and second main memory array; a first redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside of the memory device through a first redundancy bus, when a first column address indicates one or more defective columns of the first main memory array; and a second redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside through a second redundancy bus, when a second column address indicates one or more defective columns of the second main memory array.
    Type: Application
    Filed: September 11, 2012
    Publication date: November 28, 2013
    Inventor: Bo-Kyeom Kim
  • Patent number: 8547758
    Abstract: A semiconductor memory device includes a page buffer configured to store data received from selected memory cells in response to a read command, a first register configured to store first data received from the page buffer in response to a first control signal, a second register configured to store second data received from the page buffer in response to a second control signal, a data I/O circuit configured to, while the first or second data is outputted from the first register or the second register, respectively, input third data received from the page buffer to the other one of the first and second registers, and a control logic configured to sequentially supply the first control signal and the second control signal in outputting the first and second data.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: October 1, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Bo Kyeom Kim
  • Publication number: 20130141979
    Abstract: A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels.
    Type: Application
    Filed: August 30, 2012
    Publication date: June 6, 2013
    Applicant: SK HYNIX INC.
    Inventor: Bo Kyeom KIM
  • Publication number: 20120140573
    Abstract: A semiconductor memory device includes a page buffer configured to store data received from selected memory cells in response to a read command, a first register configured to store first data received from the page buffer in response to a first control signal, a second register configured to store second data received from the page buffer in response to a second control signal, a data I/O circuit configured to, while the first or second data is outputted from the first register or the second register, respectively, input third data received from the page buffer to the other one of the first and second registers, and a control logic configured to sequentially supply the first control signal and the second control signal in outputting the first and second data.
    Type: Application
    Filed: July 14, 2011
    Publication date: June 7, 2012
    Inventor: Bo Kyeom KIM