Abstract: A semiconductor memory device includes a page buffer configured to store data received from selected memory cells in response to a read command, a first register configured to store first data received from the page buffer in response to a first control signal, a second register configured to store second data received from the page buffer in response to a second control signal, a data I/O circuit configured to, while the first or second data is outputted from the first register or the second register, respectively, input third data received from the page buffer to the other one of the first and second registers, and a control logic configured to sequentially supply the first control signal and the second control signal in outputting the first and second data.

Abstract: A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels.

Abstract: A semiconductor memory device includes a page buffer configured to store data received from selected memory cells in response to a read command, a first register configured to store first data received from the page buffer in response to a first control signal, a second register configured to store second data received from the page buffer in response to a second control signal, a data I/O circuit configured to, while the first or second data is outputted from the first register or the second register, respectively, input third data received from the page buffer to the other one of the first and second registers, and a control logic configured to sequentially supply the first control signal and the second control signal in outputting the first and second data.

Abstract: A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator for reflecting in the data clock a value of subtracting an output of the delay time calculator from the information established in the mode register set.

Abstract: An apparatus for generating error detection codes can include an error detection code generation unit configured to generate virtual error detection codes using virtual DBI information and data, and an error detection code regeneration unit configured to generate error detection codes using even and odd number information which define whether the number of data associated with the generation of the error detection codes is even or odd, DBI information associated with the even and odd number information, and the virtual error detection codes.

Abstract: A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines.

Abstract: There is provided a semiconductor memory device, including: a plurality of bank groups each comprising a plurality of banks; a plurality of data pads grouped by a predetermined number for receiving data for the bank groups, wherein the data pads are divided into a plurality of first pad groups receiving data and a plurality of second pad groups selectively receiving data according to a data input/output option value; a first driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the first pad group; a second driving unit configured to drive data input via the second pad group to transfer the data input via the second pad group to the bank group corresponding to the second pad group; and a third driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the second pad group in response to the data input/output option va

Abstract: A duty correction circuit includes a duty ratio sensor for controlling a duty ratio sensing speed by a sensing speed control signal and outputting a correction signal by sensing a duty ratio of a clock, and a duty ratio corrector for controlling the duty ratio of the clock in response to the correction signal.

Abstract: A delay locked loop circuit for compensating for a phase skew of a memory device includes a first delay locking unit configured to delay an external clock of the memory device by a first amount of delay to output a first internal clock, a second locking unit configured to delay the external clock by a second amount of delay to output a second internal clock, the second amount of delay being greater than the first amount of delay, and a selecting unit configured to select one of the first internal clock and the second internal clock as an internal clock of the memory device.

Abstract: A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines.

Abstract: A duty correction circuit includes a duty ratio sensor for controlling a duty ratio sensing speed by a sensing speed control signal and outputting a correction signal by sensing a duty ratio of a clock, and a duty ratio corrector for controlling the duty ratio of the clock in response to the correction signal.

Abstract: There is provided a semiconductor memory device, including: a plurality of bank groups each comprising a plurality of banks; a plurality of data pads grouped by a predetermined number for receiving data for the bank groups, wherein the data pads are divided into a plurality of first pad groups receiving data and a plurality of second pad groups selectively receiving data according to a data input/output option value; a first driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the first pad group; a second driving unit configured to drive data input via the second pad group to transfer the data input via the second pad group to the bank group corresponding to the second pad group; and a third driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the second pad group in response to the data input/output option va

Abstract: A delay locked loop circuit for compensating for a phase skew of a memory device includes a first delay locking unit configured to delay an external clock of the memory device by a first amount of delay to output a first internal clock, a second locking unit configured to delay the external clock by a second amount of delay to output a second internal clock, the second amount of delay being greater than the first amount of delay, and a selecting unit configured to select one of the first internal clock and the second internal clock as an internal clock of the memory device.

Abstract: A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator for reflecting in the data clock a value of subtracting an output of the delay time calculator from the information established in the mode register set.

Abstract: An apparatus for generating error detection codes can include an error detection code generation unit configured to generate virtual error detection codes using virtual DBI information and data, and an error detection code regeneration unit configured to generate error detection codes using even and odd number information which define whether the number of data associated with the generation of the error detection codes is even or odd, DBI information associated with the even and odd number information, and the virtual error detection codes.