Abstract: During a read operation for memory cells connected a selected word line, a memory system adjusts the overdrive voltage applied to word lines adjacent the selected word line in order to compensate for margin degradation between the erased data state and the lowest programmed data state.

Abstract: The disclosure discloses a measuring device for dynamic characteristics of pressure sensitive paint, including a PSP sample wafer, a dynamic pressure sensor, an oscilloscope, a light source, a photomultiplier tube, a bandpass filter, a loudspeaker, a power amplifier, and a signal generator. The disclosure further discloses a measuring method for dynamic characteristics of pressure sensitive paint. The disclosure has the following beneficial effects: by using the measuring device disclosed by the present disclosure, the continuous sinusoidal pressure wave with any frequency can be generated, and has the frequency precision that does not exceed 0.01 Hz, an optical path is not shielded, high stability is achieved, and the amplitude and phase characteristics of the pressure frequency of the PSP can be precisely captured.

Abstract: A terminal device obtains first slice selection assistance information, where the first slice selection assistance information is obtained by encrypting second slice selection assistance information, and the second slice selection assistance information is selection assistance information of a slice to which the terminal device is allowed to access. The terminal device sends a registration request message to an access network device, where the registration request message includes the first slice selection assistance information.

Abstract: The present disclosure provides a direct current (DC) transformer error detection apparatus for a pulsating harmonic signal, including a DC and pulsating harmonic current output module and an external detected input module, where the DC and pulsating harmonic current output module outputs a DC and a DC superimposed pulsating harmonic current to an internal sampling circuit and a self-calibrated standard resistor array; and the internal sampling circuit converts the input DC and the input DC superimposed pulsating harmonic current into a voltage signal, and sends the voltage signal to an analog-to-digital (AD) sampling and measurement component through a front-end conditioning circuit and a detected input channel. The DC transformer error detection apparatus can complete self-calibration for measurement of the DC and the pulsating harmonic signal on a test site.

Abstract: A magnetically-isolated wireless charging assembly enabling temporary attachment by magnetism to a device requiring charge by induction includes a housing defining an accommodating space, a plurality of magnetic members disposed within the accommodating space, a wireless charging receiver covering the plurality of magnetic members, and a wireless charging receiver. The wireless charging receiver is disposed on a side of the magnetic shielding member facing the plurality of magnetic members and the magnetic shielding member prevents the magnetic field of the magnetic members extending through or beyond the shielding member.

Abstract: An innovative equipment system comprises a tap water reservoir system, a disinfectant reactor system, a pump system, a disinfection and safety door spraying system, a sewage recycling system and a sewage treatment system, wherein the tap water reservoir system is mainly configured to store tap water in advance according to actual cargo volumes and disinfection requirements, and generally in tons; and the disinfectant reactor system comprises boron-doped diamond electrode modules, a reactor indicating lamp module, a visible reactor, a smart control screen, at least one water tank and a structure protection module. The Innovative disinfection and sterilization equipment system can easily kill bacteria and viruses such as Escherichia coli, Staphylococcus aureus, Salmonella typhimurium, and new coronavirus in a short time and enhance disinfection efficiency.

Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: Embodiments of this application disclose a network key processing system, including user equipment, a security anchor network element, and an access and mobility management network element, where the security anchor network element is configured to: obtain a first key parameter from a slice selection network element, where the first key parameter includes identifier information of N network slices; generate N slice-dedicated keys based on the first key parameter; and send the N slice-dedicated keys to the corresponding N network slices respectively; the access and mobility management network element is configured to: obtain the first key parameter, and send the first key parameter to the user equipment; and the user equipment is configured to: generate the N slice-dedicated keys for the N network slices based on the first key parameter, and access the N network slices based on the generated N slice-dedicated keys.

Abstract: A memory device that dynamically adjusts the sense time to read an open block of a memory block is disclosed. The adjusted sense time is based upon various considerations, including the sense time of the closed block equivalent and the openness of the open block. This allows the memory device to maintain a fixed Vt as well as reduce failed bit count, i.e., read errors due to an insufficient sense time. Also, the dynamic adjustment of sense time can optimize system performance and increase efficiency.

Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.

Abstract: The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data states in a second programming pass. During programming of a first set of memory cells in at least one of the first and second programming passes, the controller is further configured to determine programming statuses of a second set of memory cells that is adjacent the first set of memory cells. The controller is further configured to read the first set of memory cells using a read voltage that is adjusted from a base read voltage based on the determined programming statuses of the second set of memory cells.

Abstract: A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data state of the first word line exceeds the critical voltage by a threshold. In response to the upper tail of the erased data state exceeding the critical voltage by the threshold, the controller then alternates between the first and second programming passes until the first programming pass is completed on the remaining word lines of the memory block.

Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: erase a block; verify, using a first erase verify level, that the block was properly erased; verify, using a second erase verify level, that the block was properly erased; determine whether there are any mismatches in a plurality of verify statuses between neighboring wordlines of the block from verifying the block using the second erase verify level; and identify, based on the determination, whether the block has failed.

Abstract: A network connection between a server group of a data intake and query system and each of one or more source network nodes is established. Source data at the server group is received from at least one of the one or more source network nodes via the respective network connections and transformed, by the indexer server, to timestamped data entries of machine data. A model management server detects data constraints for a security model that include a data element used by the security model and an availability requirement set. Using the timestamped data entries, the data constraints are validated, and the validation used to determine a data availability assessment of the security model.

Abstract: The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first programming pass, verify the first set of memory cells at a first set of checkpoint data states and verify the second set of memory cells at a second set of checkpoint data states that is different than the first set of checkpoint data states.

Abstract: The present disclosure relates to a method for controlling thermoplasticity and toughness of a redox-modified plant fiber, comprising following steps: (1) pretreating a plant fiber; (2) obtaining an oxidation-modified plant fiber by adding an oxidant solution, then filtering, and washing; and obtaining the redox-modified plant fiber by adding a reductant solution, then filtering, and washing; and (3) fully mixing a plasticizer with the redox-modified plant fiber; the plasticizer being a hydroxyl plasticizer, an ionic liquid plasticizer, a deep eutectic solvent, an ester plasticizer, an amine plasticizer, a glycidyl plasticizer, or an inorganic salt plasticizer. The method according to the present disclosure can improve the toughness of the redox-modified plant fiber material, reduce the processing temperature of the plant fiber material, and broaden the processing window of the plant fiber material.

Abstract: Apparatus and methods for recovery after an abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.

Abstract: Apparatuses and techniques are described for modifying program and erase parameters in a memory device in which memory cells can be operated in a single bit per cell (SLC) mode or a multiple bits per cell mode. In one approach, the stress on a set of memory cells in an SLC mode is reduced during programming and erasing when the number of program-erase cycles for the block in the SLC mode is below a threshold. For example, during programming, the program-verify voltage and program voltages can be reduced to provide a shallower than normal programming. During erasing, the erase-verify voltage can be increased while the erase voltages can be reduced to provide a shallower than normal erase. When the number of program-erase cycles for the block in the SLC mode is above the threshold, the program and erase parameters revert to a default levels.