Abstract: The memory device includes a plane with memory blocks, each with an array of memory cells that are arranged in word lines. The memory device also includes programming circuitry that is configured to, in a selected memory block, program foggy data into the memory cells of a selected word line in a first programming pass. The circuitry is also configured to, in at least one parity memory block of the plurality of memory blocks, program two bits of parity data. The circuitry is further configured to read the foggy data of the memory cells of the selected word line of the selected memory block and read the parity data of the at least one parity memory block to reconstruct user data. The circuitry is also configured to perform a second programming pass on the selected word line.

Abstract: The memory device includes an array of memory cells that are arranged in word lines and are programmed to contain data. Circuitry is configured to erase the memory cells of the memory block in an erase operation. During erase, the circuitry is configured to begin an erase operation to erase the memory cells and suspend the erase operation for a first suspension. After the first suspension is completed, the circuitry is configured to resume the erase operation. The circuitry is then configured to receive an instruction to suspend the erase operation for a second suspension and dynamically determine a minimum resume latency based on a vulnerability of the memory block to erase errors. Only after the minimum resume latency has passed following the step of resuming the erase operation after the first suspension is completed, the circuitry is configured to suspend the erase operation for the second suspension.

Abstract: An apparatus includes one or more control circuits that are configured to connect to a plurality of nonvolatile memory cells. The one or more control circuits are configured to detect a first boundary between written and unwritten portions of an open block and, in response to detecting the first boundary, check for a second boundary between written and unwritten portions of the open block in order to determine if the open block was subject to a non-uniform erase operation.

Abstract: The present application provides a method and apparatus for cross-network converged transmission based on network coding and relates to the field of communication technologies. The method initially includes selecting an encoding method based on an application type and encoding original packets to obtain a plurality of to-be-transmitted packets. A network status is obtained and a scheduling scheme is determined based on the network status. Weights of links for transmitting the plurality of to-be-transmitted packets are adjusted based on the scheduling scheme. In the present application, the encoding method is selected based on the application type such that cross-network converged transmission can be completed based on network coding. This reduces latency while improving data transmission bandwidth.

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to apply a pre-programming pulse of a pre-program voltage to a selected one and at least one neighboring one of the plurality of word lines in a pre-program operation. The control means is also configured to apply each of a series of programming pulses of a program voltage followed by verification pulses of a plurality of program verify voltages each associated with one of the plurality of data states to the selected one of the plurality of word lines to program and verify the memory cells connected thereto during each of a plurality of program loops of a program operation.

Abstract: The memory device includes an array of memory cells that are arranged in word lines and are programmed to contain data. Circuitry is configured to erase the memory cells of the memory block in an erase operation. During erase, the circuitry is configured to begin an erase operation to erase the memory cells and suspend the erase operation for a first suspension. After the first suspension is completed, the circuitry is configured to resume the erase operation. The circuitry is then configured to receive an instruction to suspend the erase operation for a second suspension and dynamically determine a minimum resume latency based on a vulnerability of the memory block to erase errors. Only after the minimum resume latency has passed following the step of resuming the erase operation after the first suspension is completed, the circuitry is configured to suspend the erase operation for the second suspension.

Abstract: The adaptive erase scheme includes erasing the memory cells of a selected memory block in at least one erase loop. During the at least one erase loop, simultaneously, an erase voltage is applied to a plurality of channels in the selected memory block, a first bias voltage is applied to the plurality of word lines of the first sub-block, and a second bias voltage is applied to the plurality of word lines of the second sub-block. The first bias voltage is different than the second bias voltage so that the memory cells of the first and second sub-blocks are erased at different speeds.

Abstract: A plant growth light and a plant growing shed, the plant growth light including a housing enclosing a chamber having an opening at least at one end; a heat dissipation member disposed within the housing and dividing the chamber into at least a heat dissipation member channel and a lighting channel; a light board disposed in the lighting channel and being thermally connected to the heat dissipation member; a fan disposed close to the opening and forcing an airflow to accelerate. The housing illuminated by the light board is translucent to enable light to irradiate plants to be supplemented with light located outside the housing, and the housing is provided with a plurality of air outlet holes spaced in an extension direction of the heat dissipation channel to enable the accelerated airflow to be blown to plants to be ventilated located outside the housing.

Abstract: An insect trapping device, which includes an insect trapping lamp and a killing structure. The insect trapping lamp includes a lamp body, a control switch, and at least two light sources. The control switch and the light sources are provided at the lamp body. The at least two light sources includes a first light source and a second light source. The first light source and the second light source emit light of different colors, and the control switch controls the first light source and the second light source to be turned on. The killing structure is detachably connected to the lamp body and is at least partially provided at an illumination area of the insect trapping lamp. A color of the killing structure corresponds to a color of light emitted by the first light source or the second light source.

Abstract: During a read operation for memory cells connected a selected word line, a memory system adjusts the overdrive voltage applied to word lines adjacent the selected word line in order to compensate for margin degradation between the erased data state and the lowest programmed data state.

Abstract: A ventilation-type UV light includes a light body, an air guide structure provided at the bottom of the light body, a UV module, a fan and two air inlets; the air guide structure and the light body enclose to form a mounting space, the UV module is installed inside the mounting space; the fan is provided inside the air guide structure, the bottom of the air guide structure is provided with air outlets, the air inlets are provided on the periphery or bottom of the ventilation-type UV light in an encircling way, and both the air inlets and the air outlets access the mounting space. Air can flow into the mounting space along the air inlets and then can be discharged downward via the air outlets after being sterilized and disinfected by the UV module in the mounting space.

Abstract: A memory device includes a memory block comprising a plurality of memory cells and control circuitry configured to perform a read level acquisition operation to determine optimal read levels for reading a plurality of data states of the plurality of memory cells. To perform the read level acquisition operation, the control circuitry is configured to supply a read level acquisition waveform to the plurality of memory cells, obtain data miss compare (DMC) values for the plurality of memory cells based on the read level acquisition waveform, and identify the optimal read levels for the plurality of data states based on the DMC values. The control circuitry is further configured to perform a read operation on the plurality of memory cells in accordance with the optimal read levels as identified based on the DMC values.

Abstract: A non-volatile memory system detects an indication of erase depth of a population of memory cells and adjusts the programming process for the memory cells based on the detected erase depth.

Abstract: A memory device includes control circuitry configured to perform an erase operation to erase memory cells of a memory block and perform an erase verify operation to verify whether the memory cells were sufficiently erased. To perform the erase operation, the control circuitry is configured to supply a first erase voltage pulse, perform the erase verify operation subsequent to supplying the first erase voltage pulse, subsequent to the erase verify operation, supply a first bias voltage to a first one of a plurality of memory strings and a second bias voltage different than the first bias voltage to a second one of a plurality of memory strings, and, while supplying the first and second bias voltages, supply a second erase voltage pulse. The second bias voltage is configured to inhibit the second erase voltage pulse supplied to the memory cells of the second one of the plurality of memory strings.

Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: erase a block; verify, using a first erase verify level, that the block was properly erased; verify, using a second erase verify level, that the block was properly erased; determine whether there are any mismatches in a plurality of verify statuses between neighboring wordlines of the block from verifying the block using the second erase verify level; and identify, based on the determination, whether the block has failed.

Abstract: An apparatus includes one or more control circuits that are configured to connect to a plurality of nonvolatile memory cells. The one or more control circuits are configured to detect a first boundary between written and unwritten portions of an open block and, in response to detecting the first boundary, check for a second boundary between written and unwritten portions of the open block in order to determine if the open block was subject to a non-uniform erase operation.

Abstract: A power regulating device and light. The power regulating device includes a mounting base provided on the light; the mounting base provided with a mounting space; variable resistance provided inside the mounting space and electrically connecting to the control power supply of the light; control switch provided inside the mounting space and electrically connecting to the control power supply of the light; regulating part, connecting to the mounting base in a flexible way and provided with the first regulating section and the second regulating section; the first regulating section connecting to the variable resistance, the second regulating section enabling switch of the state of the control switch; compared with existing technology, the light power regulating device provided with the first regulating section and the second regulating section can realize both the continuous power regulating mode and the precise power regulating mode at the same time.

Abstract: A memory device includes a memory block comprising a plurality of memory cells and control circuitry configured to perform a read level acquisition operation to determine optimal read levels for reading a plurality of data states of the plurality of memory cells. To perform the read level acquisition operation, the control circuitry is configured to supply a read level acquisition waveform to the plurality of memory cells, obtain data miss compare (DMC) values for the plurality of memory cells based on the read level acquisition waveform, and identify the optimal read levels for the plurality of data states based on the DMC values. The control circuitry is further configured to perform a read operation on the plurality of memory cells in accordance with the optimal read levels as identified based on the DMC values.