Patents by Inventor Bo Qi
Bo Qi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240133864Abstract: Disclosed are a method for determining a platelet concentration of a blood sample, a hematology system and a storage medium.Type: ApplicationFiled: December 11, 2023Publication date: April 25, 2024Applicant: SHENZHEN MINDRAY BIO-MEDICAL ELECTRONICS CO., LTD.Inventors: Huan QI, Bo YE, Wenbo ZHENG, Changsong HU, Qi YU
-
Patent number: 11953235Abstract: A low-heat-loss operation method of a line-focusing heat collection system and the line-focusing heat collection system are provided. The method includes the following steps. Solar energy is utilized to preheat a collector tube in an empty tube state, so that the collector tube is in a preheating mode. After a set preheating temperature is reached, a heat transfer working medium is injected into the collector tube. In the injection process of the heat transfer working medium, an injection section of the collector tube is converted into a focusing mode from a preheating mode. After heat collection is finished, the circulation of the heat transfer working medium is stopped, and the focusing mode of the collector tube is kept. In the drainage process of the heat transfer working medium, an emptying section of the collector tube is converted into a light heat-tracing mode from a focusing mode.Type: GrantFiled: August 31, 2023Date of Patent: April 9, 2024Assignees: Lanzhou Dacheng Technology Co., Ltd., Dunhuang Dacheng Shengneng Technology Co., Ltd.Inventors: Duowang Fan, Duojin Fan, Linggang Kong, Wenye Qi, Yulei Fan, Xiaoming Yao, Zhiyong Zhang, Bo Li, Fujun Zhao, Zhilin Liu, Guodong Wang, Wen Li, Chongchong Zhang
-
Patent number: 11953791Abstract: There are provided a display panel and a manufacturing method thereof. The display panel includes first and second display sub-panels with a gap region arranged therebetween; and a light-shielding layer at least located in the gap region, the first and second display sub-panels each include multiple pixel units arranged in an array, each pixel unit includes: a substrate; a data line on the substrate; a black matrix on a side of the data line away from the substrate, an orthographic projection of the data line on the substrate falls within that of the black matrix on the substrate, in at least one of the first and second display sub-panel, the black matrix of the pixel unit closest to the gap region and the light-shielding layer are arranged with an interval therebetween, the black matrix is located on a side of the light-shielding layer away from the gap region.Type: GrantFiled: March 29, 2023Date of Patent: April 9, 2024Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Peng Zhou, Xiaojing Qi, Bo Wu, Xiangdong Qin
-
Patent number: 11913512Abstract: A vibration suppression method for a servo motor and a load multistage drive system is provided. For a number N of fixed vibration frequencies and one vibration frequency varying with a load position existing in a multistage drive mechanism, a number of N+1 vibration suppression filters are adopted, and each filter is configured to eliminate a corresponding vibration frequency. Fixed vibration frequencies and a vibration frequency varying with a load position in a multistage drive system are measured by using an offline method, and the varied vibration frequencies are made into a two-dimensional table related to the load positions. The fixed vibration frequencies are eliminated by using fixed-frequency parameter vibration suppression filters; and the varied vibration frequencies are eliminated by using a variable-frequency parameter vibration suppression filter, and the vibration frequencies are obtained in real time according to the load positions and the two-dimensional table.Type: GrantFiled: May 13, 2019Date of Patent: February 27, 2024Assignee: NANJING ESTUN AUTOMATION COMPANYInventors: Renkai Fan, Kaifeng Yang, Dandan Qi, Wei Qian, Bo Wu
-
Patent number: 11859278Abstract: Methods of forming carbon polymer films are disclosed. Some methods are advantageously performed at lower temperatures. The substrate is exposed to a first carbon precursor to form a substrate surface with terminations based on the reactive functional groups of the first carbon precursor and exposed to a second carbon precursor to react with the surface terminations and form a carbon polymer film. Processing tools and non-transitory memories to perform the process are also disclosed.Type: GrantFiled: March 12, 2020Date of Patent: January 2, 2024Assignee: Applied Materials, Inc.Inventors: Bhaskar Jyoti Bhuyan, Mark Saly, Ahbijit Basu Mallick, Eugene Yu Jin Kong, Bo Qi
-
Publication number: 20230407468Abstract: Methods for forming defect-free gap fill materials comprising germanium oxide are disclosed. In some embodiments, the gap fill material is deposited by exposing a substrate surface to a germane precursor and an oxidant simultaneously. The germane precursor may be flowed intermittently. The substrate may also be exposed to a second oxidant to increase the relative concentration of oxygen within the gap fill material. A process for removal of germanium oxide is also disclosed.Type: ApplicationFiled: September 5, 2023Publication date: December 21, 2023Applicant: Applied Materials, Inc.Inventors: Huiyuan Wang, Susmit Singha Roy, Takehito Koshizawa, Bo Qi, Abhijit Basu Mallick
-
Patent number: 11830729Abstract: Exemplary methods of semiconductor processing may include providing a boron-and-carbon-and-nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include generating a capacitively-coupled plasma of the boron-and-carbon-and-nitrogen-containing precursor. The methods may include forming a boron-and-carbon-and-nitrogen-containing layer on the substrate. The boron-and-carbon-and-nitrogen-containing layer may be characterized by a dielectric constant below or about 3.5.Type: GrantFiled: January 8, 2021Date of Patent: November 28, 2023Assignee: Applied Materials, Inc.Inventors: Zeqing Shen, Bo Qi, Abhijit Basu Mallick, Nitin K. Ingle
-
Patent number: 11791155Abstract: Examples of the present technology include semiconductor processing methods to form diffusion barriers for germanium in a semiconductor structure. The methods may include forming a semiconductor layer stack from pairs of Si-and-SiGe layers. The Si-and-SiGe layer pairs may be formed by forming a silicon layer, and then forming the germanium barrier layer of the silicon layer. In some embodiments, the germanium-barrier layer may be less than or about 20 ?. A silicon-germanium layer may be formed on the germanium-barrier layer to complete the formation of the Si-and-SiGe layer pair. In some embodiments, the silicon layer may be an amorphous silicon layer, and the SiGe layer may be characterized by greater than or about 5 atom % germanium. Examples of the present technology also include semiconductor structures that include a silicon-germanium layer, a germanium-barrier layer, and a silicon layer.Type: GrantFiled: August 27, 2020Date of Patent: October 17, 2023Assignee: Applied Materials, Inc.Inventors: Huiyuan Wang, Susmit Singha Roy, Takehito Koshizawa, Bo Qi, Abhijit Basu Mallick, Nitin K. Ingle
-
Patent number: 11791068Abstract: A post insulator includes an insulating post including a first end and a second end that are opposite to each other, a high-voltage-end grading ring connected to the first end of the insulating post, the high-voltage-end grading ring being insulated from the insulating post, a grounding-end grading ring connected to the second end of the insulating post, the grounding-end grading ring being insulated from the insulating post, and a charge control ring disposed on an outer surface of the insulating post, the charge control ring being insulated from the insulating post, and the charge control ring being configured to accumulate surface charges.Type: GrantFiled: October 14, 2020Date of Patent: October 17, 2023Assignees: STATE GRID CORPORATION OF CHINA, SINOMA ADVANCED MATERIALS CO., LTD., NORTH CHINA ELECTRIC POWER UNIVERSITY, SINOMA JIANGXI INSULATOR AND ELECTRICITY CO., LTD.Inventors: Licheng Lu, Faqiang Yan, Bo Qi, Zhiyi Chong, Chengrong Li, Zhijun Guo, Xiao Yang, Yanxia Ding
-
Patent number: 11781218Abstract: Methods for forming defect-free gap fill materials comprising germanium oxide are disclosed. In some embodiments, the gap fill material is deposited by exposing a substrate surface to a germane precursor and an oxidant simultaneously. The germane precursor may be flowed intermittently. The substrate may also be exposed to a second oxidant to increase the relative concentration of oxygen within the gap fill material.Type: GrantFiled: December 11, 2020Date of Patent: October 10, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Huiyuan Wang, Susmit Singha Roy, Takehito Koshizawa, Bo Qi, Abhijit Basu Mallick
-
Patent number: 11732352Abstract: Hydrogen free (low-H) silicon dioxide layers are disclosed. Some embodiments provide methods for forming low-H layers using hydrogen-free silicon precursors and hydrogen-free oxygen sources. Some embodiments provide methods for tuning the stress profile of low-H silicon dioxide films. Further, some embodiments of the disclosure provide oxide-nitride stacks which exhibit reduced stack bow after anneal.Type: GrantFiled: February 11, 2021Date of Patent: August 22, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Zeqing Shen, Bo Qi, Abhijit Basu Mallick, Nitin K. Ingle
-
Patent number: 11702751Abstract: A non-conformal, highly selective liner for etch methods in semiconductor devices is described. A method comprises forming a film stack on a substrate; etching the film stack to form an opening; depositing a non-conformal liner in the opening; etching the non-conformal liner from the bottom of the opening; and selectively etching the film stack relative to the non-conformal liner to form a logic or memory hole. The non-conformal liner comprises one or more of boron, carbon, or nitrogen.Type: GrantFiled: August 10, 2020Date of Patent: July 18, 2023Assignee: Applied Materials, Inc.Inventors: Bo Qi, Huiyuan Wang, Yingli Rao, Abhijit Basu Mallick
-
Patent number: 11682554Abstract: Exemplary methods of semiconductor processing may include providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing a boron-containing precursor to the processing region of the semiconductor processing chamber. The methods may include thermally reacting the silicon-containing precursor, the carbon-containing precursor, and the boron-containing precursor at a temperature above about 250° C. The methods may include forming a silicon-and-carbon-containing layer on the substrate.Type: GrantFiled: April 20, 2021Date of Patent: June 20, 2023Assignee: Applied Materials, Inc.Inventors: Zeqing Shen, Bo Qi, Abhijit Basu Mallick
-
Patent number: 11676813Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include delivering a dopant-containing precursor with the silicon-containing precursor and the boron-containing precursor. The dopant-containing precursor may include one or more of carbon, nitrogen, oxygen, or sulfur. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-and-boron material on a substrate disposed within the processing region of the semiconductor processing chamber. The silicon-and-boron material may include greater than or about 1 at. % of a dopant from the dopant-containing precursor.Type: GrantFiled: September 18, 2020Date of Patent: June 13, 2023Assignee: Applied Materials, Inc.Inventors: Aykut Aydin, Rui Cheng, Yi Yang, Krishna Nittala, Karthik Janakiraman, Bo Qi, Abhijit Basu Mallick
-
Patent number: 11655537Abstract: Methods for filling a substrate feature with a carbon gap fill, while leaving a void, are described. Methods comprise flowing a process gas into a high density plasma chemical vapor deposition (HDP-CVD) chamber, the chamber housing a substrate having at least one feature, the process gas comprising a hydrocarbon reactant, generating a plasma, and depositing a carbon film.Type: GrantFiled: October 26, 2020Date of Patent: May 23, 2023Assignee: Applied Materials, Inc.Inventors: Zeqing Shen, Bo Qi, Abhijit Basu Mallick
-
Patent number: 11658026Abstract: Methods for depositing a silicon-containing film on a substrate are described. The method comprises heating a processing chamber to a temperature greater than or equal to 200° C.; maintaining the processing chamber at a pressure of less than or equal to 300 Torr; coflowing a silicon precursor and nitrous oxide (N2O) into the processing chamber, and depositing a conformal silicon-containing film on the substrate. The silicon-containing film has dielectric constant (k-value) in a range of from about 3.8 to about 4.0, has a breakdown voltage of greater than 8 MV/cm at a leakage current of 1 mA/cm2 and has a leakage current of less than 1 nA/cm2 at 2 MV/cm.Type: GrantFiled: October 23, 2020Date of Patent: May 23, 2023Assignee: Applied Materials, Inc.Inventors: Zeqing Shen, Bo Qi, Abhijit Basu Mallick
-
Patent number: 11626278Abstract: Exemplary methods of semiconductor processing may include providing a boron-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. The methods may include thermally reacting the boron-containing precursor and the carbon-containing precursor at a temperature below about 650° C. The methods may include forming a boron-and-carbon-containing layer on the substrate.Type: GrantFiled: March 24, 2021Date of Patent: April 11, 2023Assignee: Applied Materials, Inc.Inventors: Bo Qi, Zeqing Shen, Abhijit Basu Mallick
-
Patent number: 11545354Abstract: Exemplary processing methods may include flowing a first deposition precursor into a substrate processing region to form a first portion of an initial compound layer. The first deposition precursor may include an aldehyde reactive group. The methods may include removing a first deposition effluent including the first deposition precursor from the substrate processing region. The methods may include flowing a second deposition precursor into the substrate processing region. The second deposition precursor may include an amine reactive group, and the amine reactive group may react with the aldehyde reactive group to form a second portion of the initial compound layer. The methods may include removing a second deposition effluent including the second deposition precursor from the substrate processing region. The methods may include annealing the initial compound layer to form an annealed carbon-containing material on the surface of the substrate.Type: GrantFiled: July 22, 2020Date of Patent: January 3, 2023Assignees: Applied Materials, Inc., National University of SingaporeInventors: Bhaskar Bhuyan, Zeqing Shen, Bo Qi, Abhijit Basu Mallick, Xinke Wang, Mark Saly
-
Publication number: 20220406594Abstract: Embodiments of the present disclosure generally relate to processes for forming silicon- and boron-containing films for use in, e.g., spacer-defined patterning applications. In an embodiment, a spacer-defined patterning process is provided. The process includes disposing a substrate in a processing volume of a processing chamber, the substrate having patterned features formed thereon, and flowing a first process gas into the processing volume, the first process gas comprising a silicon-containing species, the silicon-containing species having a higher molecular weight than SiH4. The process further includes flowing a second process gas into the processing volume, the second process gas comprising a boron-containing species, and depositing, under deposition conditions, a conformal film on the patterned features, the conformal film comprising silicon and boron.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Inventors: Aykut AYDIN, Rui CHENG, Karthik JANAKIRAMAN, Abhijit B. MALLICK, Takehito KOSHIZAWA, Bo QI
-
Patent number: 11515170Abstract: Methods of etching film stacks to form gaps of uniform width are described. A film stack is etched through a hardmask. A conformal liner is deposited in the gap. The bottom of the liner is removed. The film stack is selectively etched relative to the liner. The liner is removed. The method may be repeated to a predetermined depth.Type: GrantFiled: December 30, 2020Date of Patent: November 29, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Shishi Jiang, Pramit Manna, Bo Qi, Abhijit Basu Mallick, Rui Cheng, Tomohiko Kitajima, Harry S. Whitesell, Huiyuan Wang