Patents by Inventor Bo-Rong Chen

Bo-Rong Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210013334
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.
    Type: Application
    Filed: August 7, 2019
    Publication date: January 14, 2021
    Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • Publication number: 20210009597
    Abstract: Disclosed are compounds of formula (I) below and tautomers, stereoisomers, isotopologues, or pharmaceutically acceptable salts thereof: in which each of variables R1, ring A, L, W, V, and G is defined herein. Also disclosed are a method for treating disease or disorder mediated by Tyro3, Axl, and/or Mer kinase with a compound of formula (I) or a tautomer, stereoisomer, isotopologue, or salt thereof and a pharmaceutical composition containing same.
    Type: Application
    Filed: December 26, 2018
    Publication date: January 14, 2021
    Applicant: Development Center for Biotechnology
    Inventors: Shih-Chieh YEN, Chu-Bin LIAO, Hui-Chen WANG, Po-Ting CHEN, Yu-Chih PAN, Tsung-Hui LI, Bo-Rong CHEN, Shian-Yi CHIOU
  • Patent number: 10841877
    Abstract: A management nodal point of a wireless sensor network (WSN) receives a plurality of tasks and stores the tasks in a buffer. Each of the tasks would be assigned to and executed by a corresponding one of execution nodal points of the WSN. The management nodal point records a status of each execution nodal point as an executable status or a non-executable status. Before the management nodal point assigns a first task, the management nodal point obtains the status of a first execution nodal point corresponding to the first task. If the first execution nodal point is at the executable status, the management nodal point assigns the first task to the first execution nodal point according to a predetermined rule.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: November 17, 2020
    Assignee: PEGATRON CORPORATION
    Inventors: Bo-Rong Chen, Tzu-Min Yang, Wen-Pin Li
  • Publication number: 20190166554
    Abstract: A management nodal point of a wireless sensor network (WSN) receives a plurality of tasks and stores the tasks in a buffer. Each of the tasks would be assigned to and executed by a corresponding one of execution nodal points of the WSN. The management nodal point records a status of each execution nodal point as an executable status or a non-executable status. Before the management nodal point assigns a first task, the management nodal point obtains the status of a first execution nodal point corresponding to the first task. If the first execution nodal point is at the executable status, the management nodal point assigns the first task to the first execution nodal point according to a predetermined rule.
    Type: Application
    Filed: October 1, 2018
    Publication date: May 30, 2019
    Inventors: Bo-Rong Chen, Tzu-Min Yang, Wen-Pin Li
  • Patent number: 9349728
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal-oxide semiconductor (MOS) transistor thereon and a first interlayer dielectric (ILD) layer surrounding the MOS transistor; forming a source layer, a drain layer, a first opening between the source layer and the drain layer, and a second ILD layer on the MOS transistor and the first ILD layer, wherein the top surfaces of the source layer, the drain layer, and the second ILD layer are coplanar; forming a channel layer on the second ILD layer, the source layer, and the drain layer and into the first opening; and performing a first planarizing process to remove part of the channel layer so that the top surface of the channel layer is even with the top surfaces of the source layer and the drain layer.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 24, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Fu Hsu, Bo-Rong Chen